US6373301B1
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Fast-locking dual rail digital delayed locked loop
Assignee: Silicon Integrated Systems Corp
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Filing: 2001-04-18
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Granted: 2002-04-16
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Expires: 2021-04-18
Abstract
Abstract This present invention discloses a circuit for generating a delay signal, which includes a first delay line for generating a first delay signal, a second delay line for generating a second delay signal, a delay unit for generating an internal delay signal, a first phase detector for generating a first control signal, a second phase detector for generating a second control signal. There's a delay line monitor for generating the first delay control signal and the second delay control signal, and a DTC delay unit for generating the delay signal.
Inventors
- 👤 Han-Ning Chen
- 👤 Ming-Shien Lee
- 👤 Jew-Yong Kuo
- 👤 Tsan-Hui Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:02
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0805; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/085; H03L7/087
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
161 words
A circuit for generating a delay signal, comprising: a first delay line, in response to an external clock signal and a first delay control signal, for generating a first delay signal; a second delay line, in response to a second delay control signal and the external clock signal, for generating a second delay signal; a delay unit, responsive to the external clock signal, for generating an internal delay signal; a first phase detector, responsive to the internal delay signal and the first delay signal, for generating a first control signal; a second phase detector, responsive to the internal delay signal and the second delay signal, for generating a second control signal; a delay line monitor, responsive to the first and the second control signal, for generating the first delay control signal and the second delay control signal; and a digital-to-time converter (DTC) delay unit, responsive to the external clock signal and the first delay control signal, for generating the delay signal.
Claim 2
Dependent Claim
161 words
A circuit for generating a delay signal, comprising: a first delay line, in response to an external clock signal and a first delay control signal, for generating a first delay signal; a second delay line, in response to a second delay control signal and the external clock signal, for generating a second delay signal; a delay unit, responsive to the external clock signal, for generating an internal delay signal; a first phase detector, responsive to the internal delay signal and the first delay signal, for generating a first control signal; a second phase detector, responsive to the internal delay signal and the second delay signal, for generating a second control signal; a delay line monitor, responsive to the first and the second control signal, for generating the first delay control signal and the second delay control signal; and a digital-to-time converter (DTC) delay unit, responsive to the external clock signal and the first delay control signal, for generating the delay signal.
Claim 3
Dependent Claim
27 words
The circuit of claim 1 , wherein the first delay line and the second delay line have N DTC delay units respectively, N is a predetermined number.
Claim 4
Dependent Claim
11 words
The circuit of claim 2 , wherein N equals to 4.
Claim 5
Dependent Claim
44 words
The circuit of claim 1 , wherein the internal delay signal generated by the delay unit has a delay of ½ Tres to the external clock signal, wherein Tres is a difference of timings of the first delay signal and the second delay signal.
Claim 6
Dependent Claim
23 words
The circuit of claim 1 , wherein the delay unit is further responsive to the first delay signal and the second delay signal.
Claim 7
Dependent Claim
114 words
The circuit of claim 1 , wherein the first delay control signal and the second delay control signal having initial values of k and k+1 respectively, k is a number, the delay line monitor generates the first and the second delay control signals by the steps of: if the first control signal is 1 and the second control signal is 0, decreasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1; and if the first control signal is 0 and the second control signal is 1, increasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1.
Claim 8
Dependent Claim
36 words
The circuit of claim 2 , wherein the delay signal generated by the DTC delay unit has a delay of T/N to the external clock signal, T is a cycle time of the external clock signal.
Claim 9
Dependent Claim
25 words
The circuit of claim 3 , the delay signal generated by the DTC delay unit has a delay of T/4 to the external clock signal.
Claim 10
Dependent Claim
15 words
The circuit of claim 1 , wherein the first phased detector is a D flip-flop.
Claim 11
Dependent Claim
15 words
The circuit of claim 1 , wherein the second phase detector is a D flip-flop.
Claim 12
Independent Claim
172 words
A method for generating a delay signal, comprising the following steps: (11.1) providing a first delay line, in response to an external clock signal and the first delay control signal, for generating a first delay signal; (11.2) providing a second delay line, in response to a second delay control signal, for generating a second delay signal; (11.3) providing a delay unit, responsive to the external clock signal, for generating an internal delay signal; (11.4) providing a first phase detector, responsive to internal delay signal and the first delay signal, for generating a first control signal; (11.5) providing a second phase detector, responsive to the internal delay signal and the second delay signal, for generating a second control signal; (11.6) providing a delay line monitor, responsive to the first and the second control signal, for generating the first delay control signal and the second delay control signal; and (11.7) providing a digital-to-time converter (DTC) delay unit, responsive to the external clock signal and the first delay control signal, for generating the delay signal.
Claim 13
Independent Claim
172 words
A method for generating a delay signal, comprising the following steps: (11.1) providing a first delay line, in response to an external clock signal and the first delay control signal, for generating a first delay signal; (11.2) providing a second delay line, in response to a second delay control signal, for generating a second delay signal; (11.3) providing a delay unit, responsive to the external clock signal, for generating an internal delay signal; (11.4) providing a first phase detector, responsive to internal delay signal and the first delay signal, for generating a first control signal; (11.5) providing a second phase detector, responsive to the internal delay signal and the second delay signal, for generating a second control signal; (11.6) providing a delay line monitor, responsive to the first and the second control signal, for generating the first delay control signal and the second delay control signal; and (11.7) providing a digital-to-time converter (DTC) delay unit, responsive to the external clock signal and the first delay control signal, for generating the delay signal.
Claim 14
Dependent Claim
27 words
The method of claim 11 , wherein the first delay line and the second delay line have N DTC delay units respectively, N is a predetermined number.
Claim 15
Dependent Claim
11 words
The method of claim 12 , wherein N equals to 4.
Claim 16
Dependent Claim
44 words
The method of claim 11 , wherein the internal delay signal generated by the delay unit has a delay of ½ Tres to the external clock signal, wherein Tres is a difference of timings of the first delay signal and the second delay signal.
Claim 17
Dependent Claim
23 words
The circuit of claim 11 , wherein the delay unit is further responsive to the first delay signal and the second delay signal.
Claim 18
Dependent Claim
114 words
The method of claim 11 , wherein the first delay control signal and the second delay control signal having initial values of k and k+1 respectively, k is a number, the delay line monitor generates the first and the second delay control signals by the steps of: if the first control signal is 1 and the second control signal is 0, decreasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1; and if the first control signal is 0 and the second control signal is 1, increasing the values of the first delay control signal (k) and the second delay control signal (k+1) by 1.
Claim 19
Dependent Claim
41 words
The method of claim 11 , wherein the delay signal generated by the DTC delay unit has a delay of T/N to the external clock signal, T is a cycle time of the external clock signal, N is a predetermined number.
Claim 20
Dependent Claim
25 words
The method of claim 11 , the delay signal generated by the DTC delay unit has a delay of T/4 to the external clock signal.
Claim 21
Dependent Claim
15 words
The method of claim 11 , wherein the first phased detector is a D flip-flop.
Claim 22
Dependent Claim
15 words
The method of claim 11 , wherein the second phased detector is a D flip-flop.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-04-15 | 2005-10-15 | 2006-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-04-15 | 2009-10-15 | 2010-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-04-15 | 2013-10-15 | 2014-04-16 | $7700.00 | Window Closed / Lapsed |