US6553472B2
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US
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Method for programming clock delays, command delays, read command parameter delays, and write command parameter delays of a memory controller in a high performance microprocessor
Assignee: Oracle America Inc
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Filing: 2001-01-12
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Granted: 2003-04-22
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Expires: 2021-01-12
Abstract
Abstract A method for programming a controller of a memory unit has been developed. The method includes inputting variable initialization parameters of the memory unit and a clock delay and a command delay for each parameter. Based on each pair of clock delays and command delays, calculate a set of delays for a read command and a write command. Calculate the system performance for each pair of clock and command delays bases on the read and write delays and select the initial parameters that offer optimum system performance.
Inventors
- 👤 Liuxi Yang
- 👤 Duong Tong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:20
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G06F9/00; G06F9/06; G06F9/22; G06F13/1694
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
128 words
A method for programming a controller of a memory unit comprising: inputting a plurality of initialization parameters of the memory unit; calculating a set of pairs of clock delays and command delays using the plurality of initialization parameters; calculating a set of read command parameters for each pair of clock delays and command delays; calculating a set of write command parameters for each pair of clock delays and command delays; calculating a set of system performance measures for each pair of clock delays and command delays, using the set of read command parameters and the set of write command parameters; and selecting the pair of clock delay and command delay and the set of read command parameters and write command parameters calculated therefrom that offer optimum system performance.
Claim 2
Independent Claim
128 words
A method for programming a controller of a memory unit comprising: inputting a plurality of initialization parameters of the memory unit; calculating a set of pairs of clock delays and command delays using the plurality of initialization parameters; calculating a set of read command parameters for each pair of clock delays and command delays; calculating a set of write command parameters for each pair of clock delays and command delays; calculating a set of system performance measures for each pair of clock delays and command delays, using the set of read command parameters and the set of write command parameters; and selecting the pair of clock delay and command delay and the set of read command parameters and write command parameters calculated therefrom that offer optimum system performance.
Claim 3
Dependent Claim
35 words
The method of claim 1 , wherein the plurality of initialization parameters comprises: system parameters; device parameters of a SDRAM unit; and a time period ratio of a system clock and a SDRAM unit clock.
Claim 4
Dependent Claim
16 words
The method of claim 1 , wherein the system performance comprises: bandwidth performance; and margin performance.
Claim 5
Dependent Claim
42 words
The method of claim 1 , wherein the set of read command delays comprises: a sample delay; a RAS to CAS delay; a valid extension delay; a pre-charge delay; an auto-refresh delay; and a delay for other banks after a current command.
Claim 6
Dependent Claim
42 words
The method of claim 1 , wherein the set of write command delays comprises: a push delay; a RAS to CAS delay; a valid extension delay; a pre-charge delay; an auto-refresh delay; and a delay for other banks after a current command.
Claim 7
Dependent Claim
14 words
The method of claim 1 , wherein the memory unit supports a single microprocessor.
Claim 8
Dependent Claim
15 words
The method of claim 1 , wherein the memory unit supports a plurality of microprocessors.
References Cited (Backward Citations)
US5857095A
Cited
US5886948A
Cited
EP0855653A1
Cited
US6397312B1
Cited
US6292903B1
Cited
US6073223A
Cited
US5917761A
Cited
US6389522B1
Cited
WO2000020978A1
Cited
US6137734A
Cited
US6370067B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-21 | 2006-10-21 | 2007-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-21 | 2010-10-21 | 2011-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-21 | 2014-10-21 | 2015-04-22 | $7700.00 | Window Closed / Lapsed |