EP0855653A1
Expired / Lapsed
EP
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Memory controller with a programmable strobe delay
Assignee: HP Inc
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Filing: 1997-01-23
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Granted: —
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Expires: 2017-01-23
Abstract
Abstract A memory controller is providing that has a clock line (7) for a clock signal; a data bus (2) for connecting to at least one memory module (3, 4, 5); a data latch (6) connected to the data bus (2), for latching data under control of a strobe signal; and a programmable delay (20) for providing the strobe signal in programmed timing relation to the clock signal. The programmable delay comprises, for example, a programmable delay line connected between the clock line (1) and an enabling input (9) of the data latch (6). This arrangement permits the timing of the strobe signal to be adjusted to compensate for changes in memory configuration and other system parameters.
Inventors
- 👤 Pierre-Yves Thoulon
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 20:29
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1694; G06F13/1689; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
68 words
A memory controller comprising: -- a clock line (7) for a clock signal; -- data receiving means (2) for connecting to at least one memory module (3, 4,
5); -- data latching means (6) connected to the data receiving means (2), for latching
data under control of a strobe signal; and -- programmable means (20) for providing said strobe signal in programmed
timing relation to said clock signal.
Claim 2
Dependent Claim
29 words
A memory controller according to claim 1, wherein the programmable means (20)
comprise a programmable delay operatively connected between said clock line (7) and
said data latching means (6).
Claim 3
Dependent Claim
53 words
A memory controller according to claim 1, further comprising: -- a memory control line (8) for a memory-read signal, and -- means for producing said memory-read signal in timed relation to said clock
signal; said programmable means (20) being a programmable delay operatively connected
between said memory-control line and said data latching means.
Claim 4
Dependent Claim
26 words
A memory controller according to any one of the preceding claims, wherein the
programmable means (20) comprise a programmable register for setting said
programmed timing relation.
Claim 5
Dependent Claim
32 words
A system having at least one memory module, and a memory controller according
to claim 1; said system including delay-programming means for automatically
programming the programmable means for providing the strobe signal.
Claim 6
Dependent Claim
19 words
A system according to claim 5, wherein said programming means effects said
programming upon power up of said system.
Claim 7
Dependent Claim
80 words
A system having at least one memory module and a memory controller according
to claim 1; said system including: -- first means for periodically measuring the value of a parameter indicative of the
signal delay characteristics in the system in order to detect variations therein,
and -- second means responsive to variations in said signal delay characteristics
detected by said first means, to incrementally change the programming of said
programmable means to compensate said programmed timing relation for said
variations.
Claim 8
Dependent Claim
112 words
A method for programming the programmable means in a memory controller
according to claim 1; said method, comprising the steps of: (a) - programming the programmable means to a given value; (b) - using the memory controller to write data into memory means; (c) - using the memory controller to read the data written into the memory means; (d) - determining whether the data read in step (b) are identical to the data written
in step (c); (e) - repeating steps (a) to (d) until step (d) gives a positive result for at least one
given value. (f) - programming the programmable means to one of said at least one given value.
Claim 9
Dependent Claim
37 words
A method according to claim 8, wherein step (e) comprises incrementing said given
value, and wherein, once step (d) has given a positive result, steps (a) to (d) are
repeated until step (d) gives a negative result.
Claim 10
Dependent Claim
37 words
A method according to claim 8, wherein step (e) comprises decrementing said
given value, and wherein, once step (d) has given a positive result, steps (a) to (d) are
repeated until step (d) gives a negative result.
Claim 11
Dependent Claim
28 words
A method according to claim 9 or 10, wherein step (f) comprises chosing a value
among a range of values for which step (d) gives a positive result.
Claim 12
Dependent Claim
16 words
A method according to claim 8, wherein step (e) is repeated for all possible
programmable values.
Claim 13
Dependent Claim
49 words
A method according to claim 12, wherein step (f) comprises: (g) determining ranges of values for which step (d) gives a positive result; (h) determining the largest of these ranges of values; and wherein the programmable means are programmed to a value comprised in the
largest of said ranges.
Claim 14
Independent Claim
27 words
A method for enhancing the reliability of data reading in a memory controller,
comprising programming a delay between a clock signal (10) and a reading strobe
signal.
Claim 15
Dependent Claim
18 words
A method according to claim 14, wherein said programming is carried out at
power-on of the memory controller.
Claim 16
Dependent Claim
17 words
A method according to claim 14, wherein said programming is carried out to
compensate for voltage variations.
Claim 17
Dependent Claim
19 words
A method according to claim 14, wherein said programming is carried out to
compensate for variations in processing load.
Claim 18
Dependent Claim
17 words
A method according to claim 14, wherein said programming is carried out to
compensate for temperature variations.
References Cited (Backward Citations)
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