US5560000A
Expired / Lapsed
US
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Time skewing arrangement for operating memory in synchronism with a data processor
Assignee: Texas Instruments Inc
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Filing: 1995-06-07
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Granted: 1996-09-24
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Expires: 2015-06-07
Abstract
Abstract A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.
Inventors
- 👤 Wilbur C. Vogley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:05
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
210 words
A circuit for a data processing system, the circuit comprising: an address register, interconnected with a plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory address information; a control signal register, interconnected with the plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory control signals; a data buffer register, interconnected with a memory clock delay circuit and the plurality of synchronous random access memory devices and arranged for receiving and storing data bits during a memory write operation; and the memory clock delay circuit, interconnected with the address register, the control signal register, and the plurality of synchronous random access memory devices and responsive to a system clock signal and memory clock delay data, for producing a plurality of time skewed memory clock signals each one to be applied to a separate one of the synchronous random access memory devices, and each time skewed memory clock signal being delayed a different increment of time so that the plurality of synchronous random access memory devices each can operate at a different time in response to the one of the time skewed memory clock signals to accept the address information, the control signals, and data bits.
Claim 2
Dependent Claim
210 words
A circuit for a data processing system, the circuit comprising: an address register, interconnected with a plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory address information; a control signal register, interconnected with the plurality of synchronous random access memory devices and arranged for receiving and storing synchronous random access memory control signals; a data buffer register, interconnected with a memory clock delay circuit and the plurality of synchronous random access memory devices and arranged for receiving and storing data bits during a memory write operation; and the memory clock delay circuit, interconnected with the address register, the control signal register, and the plurality of synchronous random access memory devices and responsive to a system clock signal and memory clock delay data, for producing a plurality of time skewed memory clock signals each one to be applied to a separate one of the synchronous random access memory devices, and each time skewed memory clock signal being delayed a different increment of time so that the plurality of synchronous random access memory devices each can operate at a different time in response to the one of the time skewed memory clock signals to accept the address information, the control signals, and data bits.
Claim 3
Dependent Claim
122 words
A circuit, in accordance with claim 1, wherein: the data buffer register includes a plurality of data storage devices, each data storage device being responsive to a received data bit and a write enable signal for storing the received data bit in that data storage device, and the circuit further comprising a write/read enable circuit, interconnected with the memory clock delay circuit and responsive to the system clock signal and an output enable signal, for causing the write/read enable circuit to produce plural uniformly delayed write enable signals, each write enable signal being applied to a separate data storage device to enable transmission of the stored data bits in concert from the data buffer register to the synchronous random access memory device.
Claim 4
Dependent Claim
86 words
A circuit, in accordance with claim 1, wherein: the memory clock delay circuit includes: a memory clock delay register, responsive to memory clock delay data and a memory delay data load signal, for storing the memory clock delay data to select an increment of memory clock delay time to be imparted into a memory clock signal; and a memory clock delay selector, responsive to the system clock signal and the memory clock delay data, for imparting the memory clock delay time into the memory clock signal.
Claim 5
Dependent Claim
136 words
A circuit for a data processing system, the circuit comprising: an address register arranged for receiving and storing synchronous memory address information; a control signal register arranged for receiving and storing synchronous memory control signals; a data buffer register arranged for receiving and storing data bits during a memory write operation; and a memory clock delay circuit, responsive to a system clock signal and memory clock delay data, for producing a plurality of time skewed memory clock signals, each memory clock signal being delayed a different increment of time so that a plurality of synchronous memories each can operate at a different time in response to one of the memory clock signals to receive the address information, the control signals, and data bits for writing in the data bits in coordination with the system clock signal.
Claim 6
Dependent Claim
136 words
A circuit for a data processing system, the circuit comprising: an address register arranged for receiving and storing synchronous memory address information; a control signal register arranged for receiving and storing synchronous memory control signals; a data buffer register arranged for receiving and storing data bits during a memory write operation; and a memory clock delay circuit, responsive to a system clock signal and memory clock delay data, for producing a plurality of time skewed memory clock signals, each memory clock signal being delayed a different increment of time so that a plurality of synchronous memories each can operate at a different time in response to one of the memory clock signals to receive the address information, the control signals, and data bits for writing in the data bits in coordination with the system clock signal.
Claim 7
Dependent Claim
107 words
A circuit, in accordance with claim 4, wherein: the data buffer register includes a plurality of data storage devices, each data storage device being responsive to a received data bit and a write enable signal for storing the received data bit in that data storage device, and the circuit further comprising a write/read enable circuit, responsive to the system clock signal and an output enable signal, for causing the write/read enable circuit to produce plural uniformly delayed write enable signals, each write enable signal being applied to a separate data storage device to enable transmission of the stored data bits in concert from the data buffer register.
Claim 8
Dependent Claim
85 words
A circuit, in accordance with claim 4, wherein: the memory clock delay circuit includes: a memory clock delay register, responsive to memory clock delay data and a memory delay load signal, for storing the memory clock delay data to select an increment of memory clock delay time to be imparted into a memory clock signal; and a memory clock delay selector, responsive to the system clock signal and the memory clock delay data, for imparting the memory clock delay time into the memory clock signal.
Claim 9
Dependent Claim
194 words
A circuit for a data processing system, the circuit comprising: an address register, interconnected with a plurality of synchronous memory devices and arranged for receiving and storing synchronous memory address information; a control signal register, interconnected with the plurality of synchronous memory devices and arranged for receiving and storing synchronous memory control signals; a data buffer register, interconnected with a memory clock delay circuit and the plurality of synchronous memory devices and arranged for receiving and storing data bits during a memory write operation; and the memory clock delay circuit, interconnected with the address register, the control signal register, and the plurality of synchronous memory devices and responsive to a system clock signal and memory clock delay data, for producing a plurality of time skewed memory clock signals each one to be applied to a separate one of the synchronous memory devices, and each time skewed memory clock signal being delayed a different increment of time so that the plurality of synchronous memory devices each can operate at a different time in response to the one of the time skewed memory clock signals to accept the address information, the control signals, and data bits.
Claim 10
Dependent Claim
194 words
A circuit for a data processing system, the circuit comprising: an address register, interconnected with a plurality of synchronous memory devices and arranged for receiving and storing synchronous memory address information; a control signal register, interconnected with the plurality of synchronous memory devices and arranged for receiving and storing synchronous memory control signals; a data buffer register, interconnected with a memory clock delay circuit and the plurality of synchronous memory devices and arranged for receiving and storing data bits during a memory write operation; and the memory clock delay circuit, interconnected with the address register, the control signal register, and the plurality of synchronous memory devices and responsive to a system clock signal and memory clock delay data, for producing a plurality of time skewed memory clock signals each one to be applied to a separate one of the synchronous memory devices, and each time skewed memory clock signal being delayed a different increment of time so that the plurality of synchronous memory devices each can operate at a different time in response to the one of the time skewed memory clock signals to accept the address information, the control signals, and data bits.
Claim 11
Dependent Claim
120 words
A circuit, in accordance with claim 7, wherein: the data buffer register includes a plurality of data storage devices, each data storage device being responsive to a received data bit and a write enable signal for storing the received data bit in that data storage device, and the circuit further comprising a write/read enable circuit, interconnected with the memory clock delay circuit and responsive to the system clock signal and an output enable signal, for causing the write/read enable circuit to produce plural uniformly delayed write enable signals, each write enable signal being applied to a separate data storage device to enable transmission of the stored data bits in concert from the data buffer register to the synchronous memory device.
Claim 12
Dependent Claim
86 words
A circuit, in accordance with claim 7, wherein: the memory clock delay circuit includes: a memory clock delay register, responsive to memory clock delay data and a memory delay data load signal, for storing the memory clock delay data to select an increment of memory clock delay time to be imparted into a memory clock signal; and a memory clock delay selector, responsive to the system clock signal and the memory clock delay data, for imparting the memory clock delay time into the memory clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-24 | 2000-03-25 | 2000-09-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-24 | 2004-03-25 | 2004-09-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-24 | 2008-03-25 | 2008-09-24 | $7700.00 | Window Closed / Lapsed |