EP0379772A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Programmable data transfer timing
Assignee: Digital Equipment Corp
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Filing: 1989-07-03
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Granted: —
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Expires: 2009-07-03
Abstract
Abstract A method and apparatus for providing asynchronous communication between at least one central processing unit (CPU) and at least one associated memory unit with specially programmed timing signals to latch, select and transmit data between them.
Inventors
- 👤 Michael A. Gagliardo
- 👤 John J. Lynch
- 👤 James E. Tessari
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 20:28
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F1/00; G06F1/04
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
179 words
A method of maximizing data acquisition between at least one central processing unit with a reference clock and at least one memory source, said memory source having variable data rate outputs and data paths, comprising: programming a plurality of clock delays with respect to said central processing unit reference clock to form a corresponding plurality of delayed clock signals; selecting one of said delayed clock signals for a selected one of said memory sources; signaling said selected memory source with a first latch signal synchronized with said reference clock to form latched serial source data; signaling said selected memory source with a second latch signal synchronized with said reference clock to form a plurality of latched parallel multi-bit data words from said latched serial source data; signaling said selected memory source with a select signal to select one of said latched parallel multi-bit data words; signaling said selected memory source with said selected delayed clock signal to transmit said selected multi-bit parallel data word; and reading said selected multi-bit data word during a successive cycle of said reference clock.
Claim 2
Independent Claim
179 words
A method of maximizing data acquisition between at least one central processing unit with a reference clock and at least one memory source, said memory source having variable data rate outputs and data paths, comprising: programming a plurality of clock delays with respect to said central processing unit reference clock to form a corresponding plurality of delayed clock signals; selecting one of said delayed clock signals for a selected one of said memory sources; signaling said selected memory source with a first latch signal synchronized with said reference clock to form latched serial source data; signaling said selected memory source with a second latch signal synchronized with said reference clock to form a plurality of latched parallel multi-bit data words from said latched serial source data; signaling said selected memory source with a select signal to select one of said latched parallel multi-bit data words; signaling said selected memory source with said selected delayed clock signal to transmit said selected multi-bit parallel data word; and reading said selected multi-bit data word during a successive cycle of said reference clock.
Claim 3
Dependent Claim
119 words
The method recited in claim 1, wherein said step of programming said plurality of clock delays comprises the steps of: determining the minimum transmission delay of a signal from said central processing unit to each of said memory sources; determining the minimum reception delay of each said multi-bit data word by said central processing unit from each of said memory sources; correlating each said minimum transmission delay to each of said memory sources with each of said associated minimum reception delays from each of said memory sources to establish a minimum transmission-reception delay period for each of said memory sources; and selecting the period of each of said clock delays to approximate each of said minimum transmission-reception delay periods.
Claim 4
Dependent Claim
35 words
The method recited in claim 2, wherein said step of period selecting comprises selecting one of said delayed clock signals having a delay period approximating said minimum transmission-reception delay period of said selected memory source.
Claim 5
Dependent Claim
31 words
The method recited in claim 3, wherein said step of signaling said selected memory source with said selected delayed clock signal comprises interrogating a transmit latch for said selected memory source.
Claim 6
Dependent Claim
32 words
The method recited in claim 4, wherein said step of reading said selected multi-bit data word comprises reading said multi-bit data word during a prescribed interval of said reference clock signal cycle.
Claim 7
Dependent Claim
31 words
The method recited in claim 5, wherein said step of programming said plurality of clock delays comprises programming at least one of said clock delays with a delay of substantially zero.
Claim 8
Independent Claim
297 words
A method of maximizing data acquisition between at least one central processing unit with a reference clock and at least one memory source, said memory source having variable data rate outputs and data paths, comprising the steps of: determining the minimum transmission delay of each of said data paths from said central processing unit to each of said memory sources; determining the minimum reception delay of each of said data paths by said central processing unit from each of said memory sources; correlating each of said minimum transmission delays to each of said memory sources with each of said associated minimum reception delays from each of said memory sources to establish a minimum transmission-reception delay period for each of said memory sources; programming a plurality of clock delays with respect to said central processing unit reference clock, with each said programmed delay corresponding to a different one of said minimum transmission-reception delay periods to form a plurality of delayed clock signals; selecting one of said memory sources; selecting one of said delayed clock signals having a clock delay approximating said minimum transmission-reception delay period for said selected memory source; signaling said selected memory source with a first latch signal synchronized with said reference clock signal to form latched serial source data; signaling said selected memory source with a second latch signal synchronized with said reference clock signal to form a plurality of latched parallel multi-bit data words from said latched serial source data; signaling said selected memory source with a select signal to select one of said latched parallel multi-bit data words; signaling said selected memory source with said selected delayed clock signal to transmit said selected multi-bit parallel data word; and reading said selected multi-bit data word during a successive cycle of said reference clock signal.
Claim 9
Independent Claim
297 words
A method of maximizing data acquisition between at least one central processing unit with a reference clock and at least one memory source, said memory source having variable data rate outputs and data paths, comprising the steps of: determining the minimum transmission delay of each of said data paths from said central processing unit to each of said memory sources; determining the minimum reception delay of each of said data paths by said central processing unit from each of said memory sources; correlating each of said minimum transmission delays to each of said memory sources with each of said associated minimum reception delays from each of said memory sources to establish a minimum transmission-reception delay period for each of said memory sources; programming a plurality of clock delays with respect to said central processing unit reference clock, with each said programmed delay corresponding to a different one of said minimum transmission-reception delay periods to form a plurality of delayed clock signals; selecting one of said memory sources; selecting one of said delayed clock signals having a clock delay approximating said minimum transmission-reception delay period for said selected memory source; signaling said selected memory source with a first latch signal synchronized with said reference clock signal to form latched serial source data; signaling said selected memory source with a second latch signal synchronized with said reference clock signal to form a plurality of latched parallel multi-bit data words from said latched serial source data; signaling said selected memory source with a select signal to select one of said latched parallel multi-bit data words; signaling said selected memory source with said selected delayed clock signal to transmit said selected multi-bit parallel data word; and reading said selected multi-bit data word during a successive cycle of said reference clock signal.
Claim 10
Dependent Claim
31 words
The method recited in claim 7, wherein said step of signaling said selected memory source with said selected delayed clock signal comprises interrogating a transmit latch for said selected memory source.
Claim 11
Dependent Claim
29 words
The method recited in claim 8, wherein said step of reading said selected data word comprises reading said word during a prescribed interval of said reference clock signal cycle.
Claim 12
Dependent Claim
31 words
The method recited in claim 9, wherein said step of programming said plurality of clock delays comprises programming at least one of said clock delays with a delay of substantially zero.
Claim 13
Dependent Claim
121 words
For a memory device for transferring data to at least one central processing unit with a reference clock, including a data path between said memory device and said central processing unit, a method of providing transmission of said data without synchronization of said memory device with said central processing unit, comprising the steps of: latching selected serial source data from said memory device in synchronization with said reference clock; latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; latching a selected one of said multi-bit data words; and transferring said selected one of said multi-bit data words to said central processing unit after a clock delay relative to said reference clock.
Claim 14
Dependent Claim
121 words
For a memory device for transferring data to at least one central processing unit with a reference clock, including a data path between said memory device and said central processing unit, a method of providing transmission of said data without synchronization of said memory device with said central processing unit, comprising the steps of: latching selected serial source data from said memory device in synchronization with said reference clock; latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; latching a selected one of said multi-bit data words; and transferring said selected one of said multi-bit data words to said central processing unit after a clock delay relative to said reference clock.
Claim 15
Dependent Claim
24 words
The method recited in claim 11, wherein said clock delay has a delay corresponding to a minimum transmission-reception delay period of said data path.
Claim 16
Dependent Claim
143 words
For a memory device included in a system control unit (SCU) with a reference clock adapted to work in a computer system containing multiple central processing units, said SCU including a data path between said memory device and each of said central processing units, a method of providing transmission of said data without synchronization of said memory device with said central processing units, comprising the steps of: latching selected serial source data from said memory device in synchronization with said reference clock; latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; latching a selected one of said multi-bit data words; and transferring said selected one of said multi-bit data words to each one of said central processing units after a corresponding one of a plurality of clock delays relative to said reference clock.
Claim 17
Dependent Claim
143 words
For a memory device included in a system control unit (SCU) with a reference clock adapted to work in a computer system containing multiple central processing units, said SCU including a data path between said memory device and each of said central processing units, a method of providing transmission of said data without synchronization of said memory device with said central processing units, comprising the steps of: latching selected serial source data from said memory device in synchronization with said reference clock; latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; latching a selected one of said multi-bit data words; and transferring said selected one of said multi-bit data words to each one of said central processing units after a corresponding one of a plurality of clock delays relative to said reference clock.
Claim 18
Dependent Claim
39 words
The method recited in claim 13, wherein each of said clock delays has a delay corresponding to a minimum transmission-reception delay period of said data path between said memory device and each corresponding one of said central processing units.
Claim 19
Dependent Claim
150 words
Apparatus for maximizing data acquisition between at least one central processing unit with a reference clock and at least one memory source, said memory source having variable data rate outputs and data paths, comprising: means for latching selected serial source data from a selected one of said selected memory sources in synchronization with said reference clock; means for latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; means for latching a selected one of said multi-bit data words; means for transmitting said selected multi-bit data word to said central processing unit with a selected one of a plurality of delayed clock signals, each of said delayed clock signals having a different programmed clock delay with respect to said central processing unit reference clock; and means for reading said selected multi-bit data word during a successive cycle of said reference clock.
Claim 20
Dependent Claim
150 words
Apparatus for maximizing data acquisition between at least one central processing unit with a reference clock and at least one memory source, said memory source having variable data rate outputs and data paths, comprising: means for latching selected serial source data from a selected one of said selected memory sources in synchronization with said reference clock; means for latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; means for latching a selected one of said multi-bit data words; means for transmitting said selected multi-bit data word to said central processing unit with a selected one of a plurality of delayed clock signals, each of said delayed clock signals having a different programmed clock delay with respect to said central processing unit reference clock; and means for reading said selected multi-bit data word during a successive cycle of said reference clock.
Claim 21
Dependent Claim
21 words
The apparatus recited in claim 15, wherein said means for transmitting comprises means for generating said plurality of delayed clock signals.
Claim 22
Dependent Claim
50 words
The apparatus recited in claim 16, wherein said means for generating comprises means for phasing said clock delays for each of said delayed clock signals to correspond to the minimum transmission-reception delay period of each of said data paths from said central processing unit to each of said memory sources.
Claim 23
Dependent Claim
122 words
A memory device for transferring data to at least one central processing unit with a reference clock, including a data path between said memory device and said central processing unit, providing transmission of said data without synchronization of said memory device with said central processing unit, comprising: means for latching selected serial source data from said memory device in synchronization with said reference clock; means for latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; means for latching a selected one of said multi-bit data words; and, means for transferring said selected one of said multi-bit data words to said central processing unit after a clock delay relative to said reference clock.
Claim 24
Dependent Claim
122 words
A memory device for transferring data to at least one central processing unit with a reference clock, including a data path between said memory device and said central processing unit, providing transmission of said data without synchronization of said memory device with said central processing unit, comprising: means for latching selected serial source data from said memory device in synchronization with said reference clock; means for latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; means for latching a selected one of said multi-bit data words; and, means for transferring said selected one of said multi-bit data words to said central processing unit after a clock delay relative to said reference clock.
Claim 25
Dependent Claim
25 words
The memory device recited in claim 18, wherein said clock delay has a delay corresponding to a minimum transmission-reception delay period of said data path.
Claim 26
Dependent Claim
144 words
A memory device included in a system control unit (SCU) with a reference clock adapted to work in a computer system containing multiple central processing units, said SCU including a data path between said memory device and each of said central processing units, providing transmission of said data without synchronization of said memory device with said central processing units, comprising: means for latching selected serial source data from said memory device in synchronization with said reference clock; means for latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; means for latching a selected one of said multi-bit data words; and means for transferring said selected one of said multi-bit data words to each one of said central processing units after a corresponding one of a plurality of clock delays relative to said reference clock.
Claim 27
Dependent Claim
144 words
A memory device included in a system control unit (SCU) with a reference clock adapted to work in a computer system containing multiple central processing units, said SCU including a data path between said memory device and each of said central processing units, providing transmission of said data without synchronization of said memory device with said central processing units, comprising: means for latching selected serial source data from said memory device in synchronization with said reference clock; means for latching a plurality of multi-bit data words from said latched serial source data in synchronization with said reference clock; means for latching a selected one of said multi-bit data words; and means for transferring said selected one of said multi-bit data words to each one of said central processing units after a corresponding one of a plurality of clock delays relative to said reference clock.
Claim 28
Dependent Claim
40 words
The memory device recited in claim 20, wherein each of said clock delays has a delay corresponding to a minimum transmission-reception delay period of said data path between said memory device and said corresponding one of said central processing units.
References Cited (Backward Citations)
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