Computer memory interface having a memory controller that automatically adjusts the timing of memory interface signals

Claim 2

A memory controller capable of interfacing with a memory device, wherein the controller comprises: a test unit that transmits address, control, and data write signals and receives data read signals; a transmit delay buffer that delays one of the control, address, and data write signals; a synchronous register that receives one of the data read signals; a receive buffer that delays said one of the data read signals by delaying a clock input to said synchronous register; and wherein said test unit controls the timing of the memory interface by adjusting the delays of said transmit buffer and said receive buffer.

Claim 3

The memory controller as in claim 1, wherein said test unit performs a memory test comprising a series of memory transactions, and sets the delays of said transmit delay buffer and said receive delay buffer based on the outcome of said memory test.

Claim 4

The memory controller as in claim 2 wherein said test unit comprises: a test controller that provides the address and control signals and that programs said transmit delay buffer and said receive delay buffer, wherein said test controller is capable of initiating memory transactions; a pass register coupled to said test controller and configured to record the outcome of the memory test; and wherein said test controller determines the delay settings of said transmit delay buffer and said receive delay buffer according to the value of said pass register.

Claim 5

The memory controller as in claim 3, further including: a pattern register coupled to said test controller and configured to hold data to be written to a memory device via the data write signals; and a pass logic unit coupled to said pass register and configured to determine if the data read signals match the data in said pattern register, wherein said pass logic records the outcome of the memory test into said pass register.

Claim 6

The memory controller as in claim 4 wherein said test controller performs memory tests using different delay settings of said transmit delay buffer and said receive delay buffer, said pass register records the outcome of the memory tests, and wherein said test controller adjusts the delays of said transmit delay buffer and said receive delay buffer by searching said pass register to determine which delay settings resulted in no memory errors during the memory tests.

Claim 7

The memory controller as in claim 5, wherein the test unit is capable of optimizing the delay settings at the instruction of a host computer system.

Claim 8

A memory controller capable of transmitting and receiving memory interface signals, comprising: a memory test unit that transmits and receives memory interface signals; and a programmable delay buffer that delays one of the memory interface signals, wherein said memory test unit performs memory tests using a plurality of different delay settings for said programmable buffer, detects which delay settings cause memory transaction errors, and automatically determines an optimal delay setting based on the outcome of the memory tests.

Claim 9

A memory controller capable of transmitting and receiving memory interface signals, comprising: a memory test unit that transmits and receives memory interface signals; and a programmable delay buffer that delays one of the memory interface signals, wherein said memory test unit performs memory tests using a plurality of different delay settings for said programmable buffer, detects which delay settings cause memory transaction errors, and automatically determines an optimal delay setting based on the outcome of the memory tests.

Claim 10

A memory controller capable of transmitting and receiving memory interface signals, comprising: a memory test unit that transmits and receives memory interface signals; and a programmable delay buffer that delays one of the memory interface signals, wherein said memory test unit performs memory tests using a plurality of different delay settings for said programmable buffer, detects which delay settings cause memory transaction errors, and automatically determines an optimal delay setting based on the outcome of the memory tests, and wherein said memory test unit comprises: a test control logic that performs memory tests via the memory interface signals, said test control logic further capable of adjusting the delay of said programmable buffer; a sticky register coupled to said test control logic and which comprises a flag bit associated with a predetermined delay setting of said programmable buffer, wherein said test control logic deasserts the flag bit if a memory test using the predetermined delay setting for said programmable buffer is successful; and wherein said test control logic sets the delay of said programmable buffer to the predetermined delay setting only if the flag bit is deasserted following a memory test.

Claim 11

A memory controller capable of transmitting and receiving memory interface signals, comprising: a memory test unit that transmits and receives memory interface signals; and a programmable delay buffer that delays one of the memory interface signals, wherein said memory test unit performs memory tests using a plurality of different delay settings for said programmable buffer, detects which delay settings cause memory transaction errors, and automatically determines an optimal delay setting based on the outcome of the memory tests, and wherein said memory test unit comprises: a test control logic that performs memory tests via the memory interface signals, said test control logic further capable of adjusting the delay of said programmable buffer; a sticky register coupled to said test control logic and which comprises a flag bit associated with a predetermined delay setting of said programmable buffer, wherein said test control logic deasserts the flag bit if a memory test using the predetermined delay setting for said programmable buffer is successful; and wherein said test control logic sets the delay of said programmable buffer to the predetermined delay setting only if the flag bit is deasserted following a memory test.

Claim 12

The memory controller of claim 8 wherein said memory test unit further includes: a pattern register coupled to said test unit and which holds memory write data; a pass logic unit coupled to said pattern register and which receives memory read data; and wherein said pass logic unit deasserts the flag bit if the memory read data matches the contents of said pattern register.

Claim 13

The memory controller of claim 9 wherein said memory controller is capable of receiving run instructions from a host computer to initiate a memory test.

Claim 14

The memory controller of claim 9 wherein: said memory controller comprises a plurality of programmable buffers that delay the memory interface signals; said sticky register further includes a plurality of flag bits, each of said plurality of flag bits associated with a particular combination of delay settings of said plurality of programmable buffers; said memory test unit performs memory tests using different combinations of delay settings of said plurality of programmable buffers, wherein the success of each memory test is stored in said sticky register by asserting one of said plurality of flag bits if a memory test fails; and wherein said memory test unit locates one of said plurality of flag bits that is deasserted and adjusts the delay settings of said plurality of programmable buffers according to the combination of delay settings associated with said one of said plurality of flag bits that is deasserted.

Claim 17

A The method of claim 12 wherein (c) includes asserting register bits to record memory errors.

Claim 18

The method of claim 13 wherein each of said register bits represents a set of delay values, and wherein (d) includes: searching for a register bit that is not asserted; and setting the programmable delay buffers to the delay values indicated by said register bit that is not asserted.

Claim 21

The method of claim 15 including performing a memory test for each of a plurality of delay settings.

Claim 22

The method of claim 16 including asserting a register bit associated with a particular delay setting if the memory test fails when using said particular delay setting.

Claim 23

The method of claim 17 including finding a register bit that is not asserted and programming the delays of the memory interface signals according to the delay settings associated with said register bit that is not asserted.

Claim 24

The method of claim 18 including using a first buffer to delay a signal transmitted to a memory device and a second buffer to delay signals received from a memory device, and wherein each register bit corresponds to a distinct combination of delays associated with the first and second buffers.