US6327217B1
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Variable latency buffer circuits, latency determination circuits and methods of operation thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 2000-10-05
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Granted: 2001-12-04
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Expires: 2020-10-05
Abstract
Abstract A variable delay buffer circuit, as might be used in a synchronous DRAM, includes a buffer circuit that receives an input signal and generates an output signal therefrom responsive to an output enable signal. An output enable signal generation circuit receives a latency indicating signal and generates the output enable signal responsive to a command signal with a delay that is based on the latency indicating signal. A latency interval definition circuit receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval. A latency indication circuit receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and generates the latency indicating signal therefrom. Related methods are also discussed.
Inventors
- 👤 Dae-Hyun Chung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:37
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C7/00; G11C7/22; G11C7/222; G01; G01R; G01R31/00; G01R31/28; G01R31/30; G11C7/10; G11C7/1072
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
70 words
A latency determination circuit, comprising: a latency interval definition circuit that receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval; and a latency indication circuit that receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and that generates a latency indicating signal therefrom.
Claim 2
Dependent Claim
70 words
A latency determination circuit, comprising: a latency interval definition circuit that receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval; and a latency indication circuit that receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and that generates a latency indicating signal therefrom.
Claim 3
Dependent Claim
29 words
The latency determination circuit of claim 1 , further comprising a test signal generation circuit configured to receive the clock signal and operative to produce the test signal therefrom.
Claim 4
Dependent Claim
55 words
The latency determination circuit of claim 2 , wherein the test signal generation circuit is configured to receive a control signal and to generate the test signal therefrom such that the test signal is delayed the predetermined delay with respect to a next occurring feature of the clock signal following assertion of the control signal.
Claim 5
Dependent Claim
30 words
The latency determination circuit of claim 3 , wherein the next occurring feature of the clock signal comprises an edge of the clock signal following assertion of the control signal.
Claim 6
Dependent Claim
52 words
The latency determination circuit of claim 3 , wherein the test signal generation circuit comprises: a synchronization circuit that receives the control signal and the clock signal and that generates a synchronized control signal from the control signal; and a delay circuit that produces the test signal from the synchronized control signal.
Claim 7
Dependent Claim
33 words
The latency determination circuit of claim 5 , wherein the synchronization circuit comprises a flip-flop that receives the control signal and that produces the synchronized control signal therefrom responsive to the clock signal.
Claim 8
Dependent Claim
40 words
The latency determination circuit of claim 1 , wherein the latency interval definition circuit is operative to successively generate respective edges in respective ones of a plurality of latency interval defining signals responsive to successive edges of the clock signal.
Claim 9
Dependent Claim
52 words
The latency determination circuit of claim 7 , wherein the latency interval definition circuit is responsive to a control signal and is operative to successively generate the respective edges in the respective ones of the plurality of latency interval defining signals following transition of a control signal to a predetermined logic level.
Claim 10
Dependent Claim
54 words
The latency determination circuit of claim 8 , wherein the latency interval definition circuit comprises a plurality of serially-connected flip-flops, a first one of which receives a control signal and respective ones of which generate respective ones of the plurality of latency interval defining signals from the control signal responsive to the clock signal.
Claim 11
Dependent Claim
23 words
The latency determination circuit of claim 7 , wherein the latency indication circuit is operative to produce a plurality of latency indicating signals.
Claim 12
Dependent Claim
76 words
The latency determination circuit of claim 10 , wherein the latency indication circuit is operative to assert a first latency indicating signal responsive to the test signal transitioning to a predetermined logic state before a first edge of the successively generated edges and to assert a second latency indicating signal responsive to the test signal transitioning to the predetermined logic state between the first edge and an immediately succeeding second edge of the successively generated edges.
Claim 13
Dependent Claim
92 words
The latency determination circuit of claim 10 , wherein the latency indication circuit comprises: a plurality of flip-flops that receive the clock signal at respective clock inputs thereof, that receive respective ones of the plurality of latency interval defining signals at respective data inputs thereof, and that generate respective output signals at respective data outputs from the respective latency interval defining signals responsive to the clock signal; a logic circuit that receives the plurality of output signals from the plurality of flip-flops and that generates the plurality of latency indicating signals therefrom.
Claim 14
Dependent Claim
86 words
The latency determination circuit of claim 12 , wherein the logic circuit comprises: a first inverter coupled to a data output of a first flip-flop of the plurality of flip-flops; a first NOR gate coupled to an output of the first flip-flop and a data output of a second flip-flop of the plurality of flip-flops; a second inverter coupled to the data output of the second flip-flop; and a second NOR gate coupled to a data output of a third flip-flop of the plurality of flip-flops.
Claim 15
Dependent Claim
105 words
The latency determination circuit of claim 1 : wherein the latency interval definition circuit is operative to generate an edge in a latency interval defining signal responsive to an edge of the clock signal; and wherein the latency indication circuit is operative to produce a first logic state in the latency indicating signal responsive to the test signal transitioning to a predetermined logic state before the edge of the latency interval defining signal and to produce a second logic state in the latency indicating signal responsive to the test signal transitioning to the predetermined logic state after the edge of the latency interval defining signal.
Claim 16
Dependent Claim
124 words
A variable latency buffer circuit, comprising: a buffer circuit that receives an input signal and generates an output signal therefrom responsive to an output enable signal; an output enable signal generation circuit that receives a latency-indicating signal and generates the output enable signal responsive to the command signal with a delay that is based on the latency indicating signal; a latency interval definition circuit that receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval; and a latency indication circuit that receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and that generates the latency indicating signal therefrom.
Claim 17
Dependent Claim
124 words
A variable latency buffer circuit, comprising: a buffer circuit that receives an input signal and generates an output signal therefrom responsive to an output enable signal; an output enable signal generation circuit that receives a latency-indicating signal and generates the output enable signal responsive to the command signal with a delay that is based on the latency indicating signal; a latency interval definition circuit that receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval; and a latency indication circuit that receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and that generates the latency indicating signal therefrom.
Claim 18
Dependent Claim
30 words
The variable latency buffer circuit of claim 15 , further comprising a test signal generation circuit configured to receive the clock signal and operative to produce the test signal therefrom.
Claim 19
Dependent Claim
56 words
The variable latency buffer circuit of claim 16 , wherein the test signal generation circuit is configured to receive a control signal and to generate the test signal therefrom such that the test signal is delayed the predetermined delay with respect to a next occurring feature of the clock signal following assertion of the control signal.
Claim 20
Dependent Claim
41 words
The variable latency buffer circuit of claim 15 , wherein the latency interval definition circuit is operative to successively generate respective edges in respective ones of a plurality of latency interval defining signals responsive to successive edges of the clock signal.
Claim 21
Dependent Claim
24 words
The variable latency buffer circuit of claim 18 , wherein the latency indication circuit is operative to produce a plurality of latency indicating signals.
Claim 22
Dependent Claim
77 words
The variable latency buffer circuit of claim 19 , wherein the latency indication circuit is operative to assert a first latency indicating signal responsive to the test signal transitioning to a predetermined logic state before a first edge of the successively generated edges and to assert a second latency indicating signal responsive to the test signal transitioning to the predetermined logic state between the first edge and an immediately succeeding second edge of the successively generated edges.
Claim 23
Dependent Claim
106 words
The variable latency buffer circuit of claim 15 : wherein the latency interval definition circuit is operative to generate an edge in a latency interval defining signal responsive to an edge of the clock signal; and wherein the latency indication circuit is operative to produce a first logic state in the latency indicating signal responsive to the test signal transitioning to a predetermined logic state before the edge of the latency interval defining signal and to produce a second logic state in the latency indicating signal responsive to the test signal transitioning to the predetermined logic state after the edge of the latency interval defining signal.
Claim 24
Dependent Claim
40 words
The variable latency buffer circuit of claim 15 , wherein the predetermined delay approximates a sum of a delay associated with the buffer circuit and a delay associated with a circuit that provides the input signal to the buffer circuit.
Claim 25
Dependent Claim
130 words
A memory device, comprising: an internal circuit that generates a data signal; a buffer circuit that receives the data signal and generates an output signal therefrom responsive to an output enable signal; an output enable signal generation circuit that receives a latency-indicating signal and generates the output enable signal responsive to the command signal with a delay that is based on the latency indicating signal; a latency interval definition circuit that receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval; and a latency indication circuit that receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and that generates the latency indicating signal therefrom.
Claim 26
Dependent Claim
130 words
A memory device, comprising: an internal circuit that generates a data signal; a buffer circuit that receives the data signal and generates an output signal therefrom responsive to an output enable signal; an output enable signal generation circuit that receives a latency-indicating signal and generates the output enable signal responsive to the command signal with a delay that is based on the latency indicating signal; a latency interval definition circuit that receives a clock signal and generates at least one latency interval defining signal that defines at least one latency interval; and a latency indication circuit that receives the at least one latency interval defining signal and a test signal that is delayed a predetermined delay with respect to the clock signal and that generates the latency indicating signal therefrom.
Claim 27
Dependent Claim
28 words
The memory device of claim 23 , further comprising a test signal generation circuit configured to receive the clock signal and operative to produce the test signal therefrom.
Claim 28
Dependent Claim
39 words
The memory device of claim 23 , wherein the latency interval definition circuit is operative to successively generate respective edges in respective ones of a plurality of latency interval defining signals responsive to successive edges of the clock signal.
Claim 29
Dependent Claim
75 words
The memory device of claim 25 , wherein the latency indication circuit is operative to assert a first latency indicating signal responsive to the test signal transitioning to a predetermined logic state before a first edge of the successively generated edges and to assert a second latency indicating signal responsive to the test signal transitioning to the predetermined logic state between the first edge and an immediately succeeding second edge of the successively generated edges.
Claim 30
Dependent Claim
104 words
The memory device of claim 23 : wherein the latency interval definition circuit is operative to generate an edge in a latency interval defining signal responsive to an edge of the clock signal; and wherein the latency indication circuit is operative to produce a first logic state in the latency indicating signal responsive to the test signal transitioning to a predetermined logic state before the edge of the latency interval defining signal and to produce a second logic state in the latency indicating signal responsive to the test signal transitioning to the predetermined logic state after the edge of the latency interval defining signal.
Claim 31
Dependent Claim
30 words
The memory device of claim 23 , wherein the predetermined delay approximates a sum of a delay associated with the buffer circuit and a delay associated with the internal circuit.
Claim 32
Dependent Claim
97 words
A latency determination circuit, comprising: a synchronization circuit that generates a synchronized control signal that is synchronized with a clock signal from a control signal applied thereto; a latency interval definition circuit that generates a plurality of latency interval defining signals in synchronization with the clock signal responsive to the control signal; a delay circuit that receives the synchronized control signal and generates a test signal therefrom that is delayed a predetermined delay; and a latency indication circuit that generates a plurality of latency indicating signals responsive to the latency interval defining signals and the test signal.
Claim 33
Dependent Claim
97 words
A latency determination circuit, comprising: a synchronization circuit that generates a synchronized control signal that is synchronized with a clock signal from a control signal applied thereto; a latency interval definition circuit that generates a plurality of latency interval defining signals in synchronization with the clock signal responsive to the control signal; a delay circuit that receives the synchronized control signal and generates a test signal therefrom that is delayed a predetermined delay; and a latency indication circuit that generates a plurality of latency indicating signals responsive to the latency interval defining signals and the test signal.
Claim 34
Dependent Claim
50 words
The latency determination circuit of claim 29 , wherein the predetermined delay approximates a sum of a delay time of a buffer circuit of the SDRAM, a setup time of the buffer circuit, and a delay time of a latch circuit that provides an input signal to the buffer circuit.
Claim 35
Dependent Claim
19 words
The latency determination circuit of claim 29 , wherein the latency indicating signals are provided to the buffer circuit.
Claim 36
Dependent Claim
59 words
The latency determination circuit of claim 29 , wherein the synchronization circuit comprises: a D flip-flop that receives the control signal and that produces the synchronized control signal therefrom; an inverter that receives the control signal and produces an output signal therefrom; and a transistor that deactivates the synchronized control signal responsive to the output signal of the inverter.
Claim 37
Dependent Claim
43 words
The latency determination circuit of claim 29 , wherein the latency interval definition circuit comprises a plurality of serially connected double edge triggered (DET) flip-flops clock by the clock signal, respective ones of which produce respective ones of the latency interval defining signals.
Claim 38
Dependent Claim
29 words
The latency determination circuit of claim 33 , wherein the DET flip-flops latch logic levels at their inputs in response to rising and falling edges of the clock signal.
Claim 39
Independent Claim
65 words
A method of determining latency, comprising: generating at least one latency interval defining signal from a clock signal, the at least one latency interval definition signal defining at least one latency interval; and generating a latency indicating signal from the at least one latency interval defining signal and from a test signal that is delayed with respect to the clock signal by a predetermined delay.
Claim 40
Independent Claim
65 words
A method of determining latency, comprising: generating at least one latency interval defining signal from a clock signal, the at least one latency interval definition signal defining at least one latency interval; and generating a latency indicating signal from the at least one latency interval defining signal and from a test signal that is delayed with respect to the clock signal by a predetermined delay.
Claim 41
Dependent Claim
16 words
The method of claim 35 , further comprising generating the test signal from the clock signal.
Claim 42
Dependent Claim
40 words
The method of claim 35 , wherein generating the at least one latency interval defining signal comprises successively generating respective edges in respective ones of a plurality of latency interval defining signals responsive to successive edges of the clock signal.
Claim 43
Dependent Claim
71 words
The method of claim 37 , wherein generating a latency indicating signal comprises: asserting a first latency indicating signal responsive to the test signal transitioning to a predetermined logic state before a first edge of the successively generated edges; and asserting a second latency-indicating signal responsive to the test signal transitioning to the predetermined logic state between the first edge and an immediately succeeding second edge of the successively generated edges.
Claim 44
Dependent Claim
101 words
The method of claim 35 : wherein generating at least one latency interval defining signal comprises generating an edge in a latency interval defining signal responsive to an edge of the clock signal; and wherein generating a latency indicating signal comprises: producing a first logic state in the latency indicating signal responsive to the test signal transitioning to a predetermined logic state before the edge of the latency interval defining signal; and producing a second logic state in the latency-indicating signal responsive to the test signal transitioning to the predetermined logic state after the edge of the latency interval defining signal.
Claim 45
Independent Claim
91 words
A method of determining a latency in a synchronous DRAM (SDRAM), the method comprising: generating a synchronized control signal in response to a control signal in synchronism with a clock signal; generating a plurality of latency interval defining signals responsive to the clock signal and the control signal; producing a test signal that is delayed with respect to the synchronized control signal by a predetermined delay responsive to the synchronized control signal; and generating a plurality of latency indicating signals responsive to the latency interval defining signals and the test signal.
Claim 46
Independent Claim
91 words
A method of determining a latency in a synchronous DRAM (SDRAM), the method comprising: generating a synchronized control signal in response to a control signal in synchronism with a clock signal; generating a plurality of latency interval defining signals responsive to the clock signal and the control signal; producing a test signal that is delayed with respect to the synchronized control signal by a predetermined delay responsive to the synchronized control signal; and generating a plurality of latency indicating signals responsive to the latency interval defining signals and the test signal.
Claim 47
Dependent Claim
26 words
The method of claim 40 , further comprising generating an output enable signal for a buffer circuit of the SDRAM responsive to the latency indicating signals.
Claim 48
Dependent Claim
45 words
The method of claim 41 , wherein the predetermined delay approximates a sum of a delay time of the buffer circuit, a setup time of the buffer circuit, and a delay time of a latch circuit that provides an input signal to the buffer circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-03 | 2005-06-04 | 2005-12-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-03 | 2009-06-04 | 2009-12-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-03 | 2013-06-04 | 2013-12-04 | $7700.00 | Window Closed / Lapsed |