US5568445A
Expired / Lapsed
US
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Synchronous semiconductor memory device with a write latency control function
Assignee: Samsung Electronics Co Ltd
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Filing: 1995-03-02
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Granted: 1996-10-22
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Expires: 2015-03-02
Abstract
Abstract A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.
Inventors
- 👤 Churoo Park
- 👤 Si-Yeol Lee
- 👤 Ho-Cheol Lee
- 👤 Hyun-Soon Jang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
72 words
A semiconductor memory device including a column address counter, a burst length counter and a data transfer switching circuit for processing data in synchronization with an external system clock, said semiconductor memory device comprising: means for setting a prescribed write latency value; and means for inhibiting internal operations of said column address counter, burst length counter and data transfer switching circuit for a prescribed holding time corresponding to said write latency value.
Claim 2
Dependent Claim
72 words
A semiconductor memory device including a column address counter, a burst length counter and a data transfer switching circuit for processing data in synchronization with an external system clock, said semiconductor memory device comprising: means for setting a prescribed write latency value; and means for inhibiting internal operations of said column address counter, burst length counter and data transfer switching circuit for a prescribed holding time corresponding to said write latency value.
Claim 3
Dependent Claim
45 words
The semiconductor memory device as set forth in claim 1, wherein said write latency value determines the number of clocks of said system clock counted until input data is transferred to an internal data bus from the activation of an exterior write related control signal.
Claim 4
Dependent Claim
35 words
The semiconductor memory device as set forth in claim 1, wherein outputs of said column address counter, burst length counter and data transfer switching circuit are maintained at a current state during said prescribed time.
Claim 5
Dependent Claim
21 words
The semiconductor memory device as set forth in claim 1, wherein said write latency value is set using a bonding wire.
Claim 6
Dependent Claim
20 words
The semiconductor memory device as set forth in claim 1, wherein said write latency value is set using a fuse.
Claim 7
Dependent Claim
31 words
The semiconductor memory device as set forth in claim 1, wherein said write latency value is programmed according to a signal related to an operation mode of said semiconductor memory device.
Claim 8
Dependent Claim
103 words
A semiconductor memory device including a column address counter, a burst length counter and a data transfer switching circuit, for processing data in synchronization with an external system clock, said semiconductor memory device comprising: means for generating a write latency control signal; means for generating an active information enlarged signal from a plurality of active information signals generated in response to am exterior column related control signal; and means for inhibiting internal operations of said column address counter, burst length counter and data transfer switching circuit for a prescribed holding time during which said active information enlarged signal is in an active state.
Claim 9
Dependent Claim
103 words
A semiconductor memory device including a column address counter, a burst length counter and a data transfer switching circuit, for processing data in synchronization with an external system clock, said semiconductor memory device comprising: means for generating a write latency control signal; means for generating an active information enlarged signal from a plurality of active information signals generated in response to am exterior column related control signal; and means for inhibiting internal operations of said column address counter, burst length counter and data transfer switching circuit for a prescribed holding time during which said active information enlarged signal is in an active state.
Claim 10
Dependent Claim
35 words
The semiconductor memory device as set forth in claim 7, wherein said write latency control signal delays exteriorly supplied write input data from being transferred to an internal data bus during said prescribed holding time.
Claim 11
Dependent Claim
51 words
The semiconductor memory device as set forth in claim 8, wherein said active information enlarged signal determines the number of clocks of said system clock that are counted until said exteriorly supplied input data is transferred to said internal data bus from activation of an exteriorly supplied write related control signal.
Claim 12
Dependent Claim
36 words
The semiconductor memory device as set forth in claim 7, wherein outputs of said column address counter, burst length counter and data transfer switching circuit are maintained at a current state during said prescribed holding time.
Claim 13
Dependent Claim
50 words
The semiconductor memory device as set forth in claim 7, wherein each of said plurality of active information signals has a time interval corresponding to one period of said system clock, and said active information enlarged signal is generated by a logical combination of said plurality of active information signals.
Claim 14
Dependent Claim
88 words
A semiconductor memory device including a column address counter, a burst length counter and a data transfer switching circuit for processing data in synchronization with an external system clock, said semiconductor memory device comprising: a programmable circuit which sets a prescribed write latency value; and a hold circuit which inhibiting internal operations of said column address counter, burst length counter and data transfer switching circuit for a prescribed holding time corresponding to said write latency value, said hold circuit including a chain of inverters and connected logic gates.
Claim 15
Dependent Claim
88 words
A semiconductor memory device including a column address counter, a burst length counter and a data transfer switching circuit for processing data in synchronization with an external system clock, said semiconductor memory device comprising: a programmable circuit which sets a prescribed write latency value; and a hold circuit which inhibiting internal operations of said column address counter, burst length counter and data transfer switching circuit for a prescribed holding time corresponding to said write latency value, said hold circuit including a chain of inverters and connected logic gates.
Claim 16
Dependent Claim
45 words
The semiconductor memory device as set forth in claim 1, wherein said write latency value determines the number of clocks of said system clock counted until input data is transferred to an internal data bus from the activation of an exterior write related control signal.
Claim 17
Dependent Claim
35 words
The semiconductor memory device as set forth in claim 12, wherein outputs of said column address counter, burst length counter and data transfer switching circuit are maintained at a current state during said prescribed time.
Claim 18
Dependent Claim
21 words
The semiconductor memory device as set forth in claim 12, wherein said write latency value is programmed using a bonding wire.
Claim 19
Dependent Claim
20 words
The semiconductor memory device as set forth in claim 12, wherein said write latency value is programmed using a fuse.
Claim 20
Dependent Claim
31 words
The semiconductor memory device as set forth in claim 12, wherein said write latency value is programmed according to a signal related to an operation mode of said semiconductor memory device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |