US5933379A
Expired / Lapsed
US
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Method and circuit for testing a semiconductor memory device operating at high frequency
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-03-30
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Granted: 1999-08-03
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Expires: 2018-03-30
Abstract
Abstract A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.
Inventors
- 👤 Churoo Park
- 👤 Soo-In Cho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:16
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/50; G11C29/56; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
188 words
A circuit for testing a semiconductor memory device, comprising: a latency controller synchronized with an internal clock signal for generating a latency control signal; an internal column address generator synchronized with the internal clock signal for generating a column address signal responsive to an address signal; a mode register for generating a mode signal applied to the latency controller and the internal column address generator; a column address decoder for decoding the column address signal; a memory cell selected by the column address signal for reading or writing data; an input/output control unit for controlling the data input/output from the memory cell responsive to the latency control signal; a data input buffer for storing data having a first predetermined voltage level in the memory cell; a data output buffer for retrieving data having a second predetermined voltage level from the memory cell; a frequency multiplier for receiving an external clock signal and generating the internal clock signal having a frequency "n" times a frequency of the external clock signal; and a test control unit for generating control signals necessary for controlling the frequency multiplier and the mode register.
Claim 2
Dependent Claim
188 words
A circuit for testing a semiconductor memory device, comprising: a latency controller synchronized with an internal clock signal for generating a latency control signal; an internal column address generator synchronized with the internal clock signal for generating a column address signal responsive to an address signal; a mode register for generating a mode signal applied to the latency controller and the internal column address generator; a column address decoder for decoding the column address signal; a memory cell selected by the column address signal for reading or writing data; an input/output control unit for controlling the data input/output from the memory cell responsive to the latency control signal; a data input buffer for storing data having a first predetermined voltage level in the memory cell; a data output buffer for retrieving data having a second predetermined voltage level from the memory cell; a frequency multiplier for receiving an external clock signal and generating the internal clock signal having a frequency "n" times a frequency of the external clock signal; and a test control unit for generating control signals necessary for controlling the frequency multiplier and the mode register.
Claim 3
Dependent Claim
35 words
A circuit according to claim 1 wherein the input/output control unit includes a data input multiplexer having at least two of the data input buffers for inputting at least two data signals to the multiplexer.
Claim 4
Dependent Claim
27 words
A circuit according to claim 2 wherein a first of the at least two data signals is clocked into the multiplexer according to the external clock signal.
Claim 5
Dependent Claim
27 words
A circuit according to claim 2 wherein a second of the at least two data signals is clocked into the multiplexer according to the internal clock signal.
Claim 6
Dependent Claim
18 words
A circuit according to claim 4 including a delay circuit coupling the second data signal into the multiplexer.
Claim 7
Dependent Claim
116 words
A circuit according to claim 1 wherein the frequency multiplier includes: a clock divider circuit having the external clock signal as an input and at least four outputs including a first output corresponding to the external clock signal, a second delayed output, and third and fourth delayed outputs; and a multiplication factor controller for outputting a selected one of: a) the first output at the frequency of the external clock; b) the first output and second, delayed output combined to a frequency of twice the frequency of the external clock; and c) the first output and the third and fourth delayed outputs combined to a frequency of three times the frequency of the external clock frequency.
Claim 8
Dependent Claim
52 words
A circuit according to claim 1 wherein the semiconductor memory device has multi-data input/output, the circuit including; means for synchronizing parallel input data with internally increased frequency of the memory device to multiple data in series; and means for collecting data generated in synchronism with the multiple data to output in parallel.
Claim 9
Dependent Claim
54 words
A circuit according to claim 1 wherein the test control unit includes: a master control pulse generator for generating a mode register set signal and a test mode set signal responsive to a master signal; and a frequency control signal generator for generating a frequency control signal responsive to the test mode set signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-02 | 2003-02-01 | 2003-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-02 | 2007-02-01 | 2007-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-02 | 2011-02-01 | 2011-08-03 | $7700.00 | Window Closed / Lapsed |