SDRAM clocking test mode

Claim 2

A test circuit for providing a test clock signal to a SDRAM of the type having an internal clock input, the test circuit and the SDRAM being housed in a common package having a clock terminal adapted to receive a clock signal, a clock enable terminal adapted to receive a clock enable signal, and a test enable terminal adapted to receive a test enable signal, the test circuit comprising a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the test enable terminal of the package, and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active and the test enable signal being inactive, the logic circuit deriving the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the test enable signal is active, the test clock signal having a frequency that is greater than the frequencies of the periodic signals.

Claim 3

The test circuit of claim 1 wherein the frequencies of the respective periodic signals are equal.

Claim 4

The test circuit of claim 2 wherein the periodic signal applied to the clock enable terminal is phase shifted relative to the periodic signal applied to the clock terminal.

Claim 5

The test circuit of claim 3 wherein the frequency of the test clock signal is twice the frequency of the periodic signals.

Claim 6

A test circuit for providing a test clock signal to a SDRAM of the type having an internal clock input, the test circuit and the SDRAM being housed in a common package having a clock terminal adapted to receive a clock signal, a clock enable terminal adapted to receive a clock enable signal and at least one additional terminal adapted to receive an additional signal, the test circuit comprising a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the additional terminal of the package, and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active and the additional terminal receiving a first signal, the logic circuit deriving the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the additional terminal receives a second signal, the test clock signal having a frequency that is greater than the frequencies of either of the periodic signals.

Claim 7

A test circuit for providing a test clock signal to a SDRAM of the type having an internal clock input, the test circuit and the SDRAM being housed in a common package having a clock terminal adapted to receive a clock signal, a clock enable terminal adapted to receive a clock enable signal and at least one additional terminal adapted to receive an additional signal, the test circuit comprising a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the additional terminal of the package, and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active and the additional terminal receiving a first signal, the logic circuit deriving the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the additional terminal receives a second signal, the test clock signal having a frequency that is greater than the frequencies of either of the periodic signals.

Claim 8

The test circuit of claim 5 wherein the frequencies of the respective periodic signals are equal.

Claim 9

The test circuit of claim 6 wherein the respective periodic signals are phase shifted by predetermined magnitudes relative to the periodic signal applied to the clock terminal.

Claim 10

The test circuit of claim 7 wherein the frequency of the test clock signal is the frequency of the periodic signals.

Claim 11

A test circuit for providing a test clock signal to a SDRAM of the type having an internal clock input, the test circuit and the SDRAM being housed in a common package having a clock terminal adapted to receive a clock signal and a clock enable terminal adapted to receive a clock enable signal, the test circuit comprising a logic circuit having inputs coupled to the clock terminal and the clock enable terminal and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active, and the logic circuit deriving the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the respective periodic signals are applied to the clock and clock enable terminals, the test clock signal having a frequency that is greater than the frequencies of the periodic signals.

Claim 12

A test circuit for providing a test clock signal to a SDRAM of the type having an internal clock input, the test circuit and the SDRAM being housed in a common package having a clock terminal adapted to receive a clock signal and a clock enable terminal adapted to receive a clock enable signal, the test circuit comprising a logic circuit having inputs coupled to the clock terminal and the clock enable terminal and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active, and the logic circuit deriving the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the respective periodic signals are applied to the clock and clock enable terminals, the test clock signal having a frequency that is greater than the frequencies of the periodic signals.

Claim 13

The test circuit of claim 9 wherein the frequencies of the respective periodic signals are equal.

Claim 14

The test circuit of claim 10 wherein the respective periodic signals are phased shifted by predetermined magnitudes relative to the periodic signal applied to the clock terminal.

Claim 15

The test circuit of claim 11 wherein the frequency of the test clock signal is an integer multiple of the frequency of the periodic signals.

Claim 16

A test circuit which provides either an external clock signal or a high frequency test clock signal to an internal clock input of an SDRAM, the test circuit and the SDRAM being housed in a common package, comprising: an external clock terminal for receiving the external clock signal; a clock enable terminal for receiving a clock enable signal; a test enable terminal for receiving a test enable signal; a first buffer circuit having an input terminal coupled to the external clock terminal operable to couple the external clock terminal to an output terminal in response to a buffer enable signal on a buffer enable terminal; an enable circuit having an input terminal coupled to the test enable terminal for receiving the test enable signal, an input terminal coupled to the clock enable terminal for receiving the clock enable signal, and an output terminal coupled to the buffer enable terminal of the first buffer circuit, the enable circuit operable to provide the buffer enable signal on the output terminal in response to at least one of the test enable signal and the clock enable signal being active; a frequency multiplier circuit coupled to the output terminal of the first buffer circuit for receiving a first periodic signal having a first frequency applied to the external clock terminal and coupled to the clock enable terminal for receiving a second periodic signal having a second frequency applied to the clock enable terminal, the frequency multiplier circuit operable to provide on an output terminal the high frequency test clock signal derived from the first and second periodic signals, the high frequency test clock signal having a third frequency which is greater than the first and second frequencies; a first transmission circuit having an input terminal coupled to the output terminal of the first buffer circuit, an enable terminal coupled to the test enable terminal, and an output terminal coupled to the internal clock input of the SDRAM, the first transmission circuit operable to couple the output terminal of the first buffer circuit to the internal clock input of the SDRAM in response to the test enable signal being inactive; and a second transmission circuit having an input terminal coupled to the output terminal of the frequency multiplier circuit, an enable terminal coupled to the test enable terminal and an output terminal coupled to the internal clock input of the SDRAM, the second transmission circuit operable to couple the output terminal of the frequency multiplier circuit to the internal clock input of the SDRAM in response to the test enable signal being active.

Claim 17

A test circuit which provides either an external clock signal or a high frequency test clock signal to an internal clock input of an SDRAM, the test circuit and the SDRAM being housed in a common package, comprising: an external clock terminal for receiving the external clock signal; a clock enable terminal for receiving a clock enable signal; a test enable terminal for receiving a test enable signal; a first buffer circuit having an input terminal coupled to the external clock terminal operable to couple the external clock terminal to an output terminal in response to a buffer enable signal on a buffer enable terminal; an enable circuit having an input terminal coupled to the test enable terminal for receiving the test enable signal, an input terminal coupled to the clock enable terminal for receiving the clock enable signal, and an output terminal coupled to the buffer enable terminal of the first buffer circuit, the enable circuit operable to provide the buffer enable signal on the output terminal in response to at least one of the test enable signal and the clock enable signal being active; a frequency multiplier circuit coupled to the output terminal of the first buffer circuit for receiving a first periodic signal having a first frequency applied to the external clock terminal and coupled to the clock enable terminal for receiving a second periodic signal having a second frequency applied to the clock enable terminal, the frequency multiplier circuit operable to provide on an output terminal the high frequency test clock signal derived from the first and second periodic signals, the high frequency test clock signal having a third frequency which is greater than the first and second frequencies; a first transmission circuit having an input terminal coupled to the output terminal of the first buffer circuit, an enable terminal coupled to the test enable terminal, and an output terminal coupled to the internal clock input of the SDRAM, the first transmission circuit operable to couple the output terminal of the first buffer circuit to the internal clock input of the SDRAM in response to the test enable signal being inactive; and a second transmission circuit having an input terminal coupled to the output terminal of the frequency multiplier circuit, an enable terminal coupled to the test enable terminal and an output terminal coupled to the internal clock input of the SDRAM, the second transmission circuit operable to couple the output terminal of the frequency multiplier circuit to the internal clock input of the SDRAM in response to the test enable signal being active.

Claim 18

The test circuit of claim 13 wherein the second frequency is equal to the first frequency.

Claim 19

The test circuit of claim 14 wherein the second signal is phase shifted relative to the first signal by a magnitude of 90 degrees.

Claim 20

The test circuit of claim 15 wherein the frequency multiplier circuit comprises: a first inverter having an input terminal coupled to the clock enable terminal for receiving the clock enable signal operable to provide on an output terminal an inverted clock enable signal; a second inverter having an input terminal coupled to the output terminal of the first buffer circuit for receiving the external clock signal operable to provide on an output terminal an inverted external clock signal; and an exclusive NOR gate having a first input terminal coupled to the output terminal of the first buffer circuit, a second input terminal coupled to the output terminal of the first inverter, a third input terminal coupled to the clock enable terminal, and a fourth input terminal coupled to the output terminal of the second inverter, the exclusive NOR gate providing the high frequency test clock signal on an output terminal in response to the signals on its input terminals.

Claim 21

The test circuit of claim 14 wherein the second signal is phase shifted relative to the first signal by a magnitude of 180 degrees.

Claim 22

The test circuit of claim 17 wherein the frequency multiplier circuit comprises: a first one-shot circuit having a trigger input coupled to the output terminal of the first buffer circuit which provides a first one-shot signal on an output terminal in response to a rising edge of the first periodic signal; a second one-shot circuit having a trigger input coupled to the clock enable terminal which provides a second one-shot signal on an output terminal in response to a rising edge of the second periodic signal; and an OR gate having a first input terminal coupled to the output terminal of the first one-shot circuit and a second input terminal coupled to the output terminal of the second one-shot circuit, the OR gate providing the high frequency test clock signal on an output terminal.

Claim 23

The test circuit of claim 18 wherein the duration of each of the one-shot signals is equal to one fourth the period defined by the first frequency of the first periodic signal.

Claim 24

The test circuit of claim 13 wherein the first transmission circuit comprises a transmission gate having first and second complementary input terminals, the first complementary input terminal being coupled directly to the test enable terminal and the test enable terminal being coupled through an inverter to the second complementary input terminal.

Claim 25

The test circuit of claim 20 wherein the second transmission circuit comprises a transmission gate having first and second complementary input terminals, the second complementary input terminal being coupled directly to the test enable terminal and the test enable terminal being coupled through an inverter to the first complementary input terminal.

Claim 26

The test circuit of claim 13 wherein the enable circuit comprises a NOR gate.

Claim 27

An SDRAM of the type having an internal clock input, comprising: an address bus; a control bus; a data bus; a clock terminal adapted to receive a clock signal; a clock enable terminal adapted to receive a clock enable signal; a test enable terminal adapted to receive a test enable signal; an address decoder coupled to the address bus; a control logic circuit coupled the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, the control logic circuit, and the read/write circuit, including a plurality of row lines; a plurality of pairs of first and second complementary digit lines; an array of memory cells that each have a control terminal coupled to one of the row lines and a data terminal coupled to one of the first and second complementary digit lines of one of the pairs of complementary digit lines; and a test circuit comprising a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the test enable terminal and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active and the test enable signal being inactive, the logic circuit deriving a test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the test enable signal is active, the test clock signal having a frequency that is greater than the frequencies of the periodic signals.

Claim 28

An SDRAM of the type having an internal clock input, comprising: an address bus; a control bus; a data bus; a clock terminal adapted to receive a clock signal; a clock enable terminal adapted to receive a clock enable signal; a test enable terminal adapted to receive a test enable signal; an address decoder coupled to the address bus; a control logic circuit coupled the control bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, the control logic circuit, and the read/write circuit, including a plurality of row lines; a plurality of pairs of first and second complementary digit lines; an array of memory cells that each have a control terminal coupled to one of the row lines and a data terminal coupled to one of the first and second complementary digit lines of one of the pairs of complementary digit lines; and a test circuit comprising a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the test enable terminal and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active and the test enable signal being inactive, the logic circuit deriving a test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the test enable signal is active, the test clock signal having a frequency that is greater than the frequencies of the periodic signals.

Claim 29

The SDRAM of claim 23 wherein the frequencies of the respective periodic signals are equal.

Claim 30

The SDRAM of claim 24 wherein the periodic signal applied to the clock enable terminal is phase shifted relative to the periodic signal applied to the clock terminal.

Claim 31

The SDRAM of claim 25 wherein the frequency of the test clock signal is twice the frequency of the periodic signals.

Claim 32

The SDRAM of claim 23 wherein each memory cell comprises: a storage element having a first storage terminal and a second storage terminal, the second storage terminal coupled to a reference voltage source of approximately V cc /2; and a memory switch circuit having a control terminal coupled to an associated row line, a first data terminal coupled to the first storage terminal of the storage element, and a second data terminal coupled to one of the associated first and second complementary digit lines.

Claim 33

A computer system, comprising: a data input device; a data output device; an address bus; a data bus; a control bus; and computing circuitry coupled to the data input and output devices, and the data, address, and control busses, the computing circuitry including an SDRAM of the type having an internal clock input, the SDRAM having a test circuit for providing a test clock signal to the SDRAM, the test circuit and the SDRAM being housed in a common package having a clock terminal adapted to receive a clock signal, a clock enable terminal adapted to receive a clock enable signal, and a test enable terminal adapted to receive a test enable signal, the test circuit comprising a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the test enable terminal of the package, and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active and the test enable signal being inactive, the logic circuit deriving the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the test enable signal is active, the test clock signal having a frequency that is greater than the frequencies of the periodic signals.

Claim 34

A computer system, comprising: a data input device; a data output device; an address bus; a data bus; a control bus; and computing circuitry coupled to the data input and output devices, and the data, address, and control busses, the computing circuitry including an SDRAM of the type having an internal clock input, the SDRAM having a test circuit for providing a test clock signal to the SDRAM, the test circuit and the SDRAM being housed in a common package having a clock terminal adapted to receive a clock signal, a clock enable terminal adapted to receive a clock enable signal, and a test enable terminal adapted to receive a test enable signal, the test circuit comprising a logic circuit having inputs coupled to the clock terminal, the clock enable terminal, and the test enable terminal of the package, and an output coupled to the internal clock input of the SDRAM, the logic circuit coupling the clock terminal to the output of the logic circuit responsive to the clock enable signal being active and the test enable signal being inactive, the logic circuit deriving the test clock signal from respective periodic signals applied to the clock and clock enable terminals and applying the test clock signal to the output of the logic circuit when the test enable signal is active, the test clock signal having a frequency that is greater than the frequencies of the periodic signals.

Claim 35

The system of claim 28 wherein the frequencies of the respective periodic signals are equal.

Claim 36

The system of claim 29 wherein the periodic signal applied to the clock enable terminal is phase shifted by a magnitude of 90 degrees relative to the periodic signal applied to the clock terminal.

Claim 37

The system of claim 30 wherein the frequency of the test clock signal is twice the frequency of the periodic signals.

Claim 40

The method of claim 32 wherein the frequencies of the respective periodic signals are equal.

Claim 41

The method of claim 33 wherein the periodic signal applied to the clock enable terminal is phase shifted relative to the periodic signal applied to the clock terminal.

Claim 42

The method of claim 34 wherein the frequency of the test clock signal is twice the frequency of the periodic signals.

Claim 45

The method of claim 36 wherein the frequencies of the respective periodic signals are equal.

Claim 46

The method of claim 37 wherein the periodic signal applied to the clock enable terminal is phase shifted relative to the periodic signal applied to the clock terminal.

Claim 47

The method of claim 38 wherein the frequency of the test clock signal is twice the frequency of the periodic signals.