US5384750A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data output buffer of a synchronous semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-10-04
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Granted: 1995-01-24
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Expires: 2013-10-04
Abstract
Abstract A data output buffer is used for a synchronous semiconductor memory device carrying out a data read/write operation in synchronism with an externally supplied clock. The semiconductor memory device includes a first shift register having a plurality of clock stages for transmitting a RAS signal in response to the clock; a circuit for extracting a data output margin signal from a predetermined stage among the stages of the first shift circuit; first latch circuits each receiving the data output margin signal, for generating a plurality of first latency signals having information on the RAS signal by combining row address signals and the signals extracted from the respective clock stages of the first shift circuit; a second shift circuit having a plurality of clock stages for transmitting a CAS signal in response to the clock; second latch circuits each receiving the data output margin signal, for generating a plurality of second latency signals having information on the CAS signal by combining column address signals and the signals extracted from the respective clock stages of the second shift circuit; and a latency combination circuit receiving the first and second latency signals, for generating a data output control signal to the data output buffer, so that the data output buffer can generate data output even during a RAS precharge cycle.
Inventors
- 👤 Ho-Cheol Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/22
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
145 words
A synchronous semiconductor memory device comprising: memory means for storing data; data output buffer means for outputting data stored in the memory means in response to a data output buffer control signal; and latent signal processing means responsive to a clock signal, an address strobe signal and a combination signal for generating said data output buffer control signal to control the outputting of data from said data output buffer, wherein the data output buffer control signal generated by said latent signal processing means is in sync with said clock signal, and is active for at least a first period when said address strobe signal is active as well as for at least a second period during a memory precharge period when said address strobe signal is inactive, said data output buffer outputting data stored in said memory means during both said first and second periods.
Claim 2
Dependent Claim
145 words
A synchronous semiconductor memory device comprising: memory means for storing data; data output buffer means for outputting data stored in the memory means in response to a data output buffer control signal; and latent signal processing means responsive to a clock signal, an address strobe signal and a combination signal for generating said data output buffer control signal to control the outputting of data from said data output buffer, wherein the data output buffer control signal generated by said latent signal processing means is in sync with said clock signal, and is active for at least a first period when said address strobe signal is active as well as for at least a second period during a memory precharge period when said address strobe signal is inactive, said data output buffer outputting data stored in said memory means during both said first and second periods.
Claim 3
Dependent Claim
21 words
A synchronous semiconductor memory device as defined in claim 1, wherein said address strobe signal is a row address strobe signal.
Claim 4
Dependent Claim
21 words
A synchronous semiconductor memory device as defined in claim 1, wherein said address strobe signal is a column address strobe signal.
Claim 5
Dependent Claim
23 words
A synchronous semiconductor memory device as defined in claim 1, wherein said address strobe signal includes both row and column address strobe signals.
Claim 6
Dependent Claim
20 words
A synchronous semiconductor memory device as defined in claim 1, wherein said clock signal is supplied from an external source.
Claim 7
Dependent Claim
19 words
A synchronous semiconductor memory device as defined in claim 1, wherein said combination signal is an address combination signal.
Claim 8
Dependent Claim
101 words
A synchronous semiconductor memory device including a data output buffer operating under the control of an address strobe signal and a clock signal, comprising: shifting means including a plurality of clock stages for shifting said address strobe signal therethrough under the control of said clock signal; means for extracting a data output margin signal from a predetermined node of one of said clock stages; and means, responsive to said data output margin signal, input address signals, and outputs from said clock stages, for generating a data output buffer control signal to control the output of data from said data output buffer.
Claim 9
Dependent Claim
101 words
A synchronous semiconductor memory device including a data output buffer operating under the control of an address strobe signal and a clock signal, comprising: shifting means including a plurality of clock stages for shifting said address strobe signal therethrough under the control of said clock signal; means for extracting a data output margin signal from a predetermined node of one of said clock stages; and means, responsive to said data output margin signal, input address signals, and outputs from said clock stages, for generating a data output buffer control signal to control the output of data from said data output buffer.
Claim 10
Dependent Claim
71 words
A synchronous semiconductor memory device as defined in claim 7, wherein said data output buffer control signal is active for at least a first period when said address strobe signal is active as well as for at least a second period during a memory precharge period when said address strobe signal is inactive, said data output buffer outputting data stored in said memory means during both said first and second periods.
Claim 11
Dependent Claim
20 words
A synchronous semiconductor memory device as defined in claim 7, wherein said clock signal is supplied from an external source.
Claim 12
Dependent Claim
210 words
A synchronous semiconductor memory device including a data output buffer operating under the control of a row address strobe signal and a column address strobe signal, comprising: first shifting means having a plurality of clock stages for shifting said row address strobe signal therethrough in response to a clock signal; means for extracting a data output margin signal from a predetermined stage among the clock stages of said first shifting means; first combining means for generating a plurality of first latency signals in response to row address signals, signals output from said clock stages of said first shifting means, as well as on the basis of said data output margin signal; second shifting means having a plurality of clock stages for shifting said column address strobe signal therethrough in response to said clock signal; second combining means for generating a plurality of second latency signals in response to column address signals, signals output from said clock stages of said second shifting means, as well as on the basis of said data output margin signal; and third combining means responsive to said first and second latency signals for generating a data output buffer control signal to said data output buffer to control the output of data from said data output buffer.
Claim 13
Dependent Claim
210 words
A synchronous semiconductor memory device including a data output buffer operating under the control of a row address strobe signal and a column address strobe signal, comprising: first shifting means having a plurality of clock stages for shifting said row address strobe signal therethrough in response to a clock signal; means for extracting a data output margin signal from a predetermined stage among the clock stages of said first shifting means; first combining means for generating a plurality of first latency signals in response to row address signals, signals output from said clock stages of said first shifting means, as well as on the basis of said data output margin signal; second shifting means having a plurality of clock stages for shifting said column address strobe signal therethrough in response to said clock signal; second combining means for generating a plurality of second latency signals in response to column address signals, signals output from said clock stages of said second shifting means, as well as on the basis of said data output margin signal; and third combining means responsive to said first and second latency signals for generating a data output buffer control signal to said data output buffer to control the output of data from said data output buffer.
Claim 14
Dependent Claim
71 words
A synchronous semiconductor memory device as defined in claim 10, wherein said data output buffer control signal is active for at least a first period when said address strobe signal is active as well as for at least a second period during a memory precharge period when said address strobe signal is inactive, said data output buffer outputting data stored in said memory means during both said first and second periods.
Claim 15
Dependent Claim
24 words
A semiconductor memory device as defined in claim 11, wherein said clock signal is supplied from an external source of the semiconductor memory device.
References Cited (Backward Citations)
US4719601A
Cited
US5287327A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |