US5384735A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data output buffer of a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-10-04
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Granted: 1995-01-24
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Expires: 2013-10-04
Abstract
Abstract A semiconductor memory device using a clock of a constant period supplied from the exterior of a memory chip and a sense amplifier for reading out data from a memory cell designated by an address includes at least two different delay circuits for setting at least two delay time periods from the clock, a selecting circuit for receiving signals generated from the delay circuits and selecting one of said signals by a given control signal, and a data output buffer for receiving the data generated from the sense amplifier by a signal generated from the selecting circuit.
Inventors
- 👤 Churoo Park
- 👤 Yun-ho Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:11
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106; G11C7/22
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
94 words
A semiconductor memory device data output circuit using an externally supplied clock of a constant period comprising: a delay circuit which outputs different first and second delayed signals from said clock having first and second delay time periods; a selecting circuit for receiving said first and second delayed signals generated from said delay circuit and selecting one of said first and second delayed signals according to a predetermined control signal; and a data output buffer for outputting data in response to said selected delayed signal from said selecting circuit and a latency information signal.
Claim 2
Dependent Claim
94 words
A semiconductor memory device data output circuit using an externally supplied clock of a constant period comprising: a delay circuit which outputs different first and second delayed signals from said clock having first and second delay time periods; a selecting circuit for receiving said first and second delayed signals generated from said delay circuit and selecting one of said first and second delayed signals according to a predetermined control signal; and a data output buffer for outputting data in response to said selected delayed signal from said selecting circuit and a latency information signal.
Claim 3
Dependent Claim
23 words
The semiconductor memory device data output circuit according to claim 1, wherein said predetermined control signal is derived from the combination of addresses.
Claim 4
Dependent Claim
19 words
The claim 1, wherein said selected delayed signal from said selecting circuit is synchronized with said externally supplied clock.
Claim 5
Dependent Claim
98 words
A control circuit for a semiconductor memory device receiving an externally supplied clock of a constant period and an address strobe signal and having a data output buffer, comprising: signal generating means for generating a signal for controlling data output to said data buffer in response to said clock and a latency information signal said signal generating means including at least two delay means for setting at least two different delay time periods from said clock; and selecting means for receiving signals generated from said delay means and selecting one of said signals by a given control signal.
Claim 6
Dependent Claim
98 words
A control circuit for a semiconductor memory device receiving an externally supplied clock of a constant period and an address strobe signal and having a data output buffer, comprising: signal generating means for generating a signal for controlling data output to said data buffer in response to said clock and a latency information signal said signal generating means including at least two delay means for setting at least two different delay time periods from said clock; and selecting means for receiving signals generated from said delay means and selecting one of said signals by a given control signal.
Claim 7
Dependent Claim
21 words
The semiconductor memory device as claimed in claim 4, wherein said given control signal is derived from the combination of addresses.
Claim 8
Dependent Claim
22 words
The semiconductor memory device as claimed in claim 4, wherein said signal selected by said selecting means is synchronized with said clock.
Claim 9
Dependent Claim
108 words
A semiconductor memory device receiving a clock of a constant period supplied from the exterior of a semiconductor memory chip and having a sense amplifier for reading out data from a memory cell designated by an address, comprising: at least two delay means, each delay means setting a different delay time period from said clock and delaying said clock; selecting means for receiving signals generated from said delay means and selecting one of said signals by a given control signal; and a data output buffer for receiving the data generated from said sense amplifier in response a signal generated from said selecting means and a latency information signal.
Claim 10
Dependent Claim
108 words
A semiconductor memory device receiving a clock of a constant period supplied from the exterior of a semiconductor memory chip and having a sense amplifier for reading out data from a memory cell designated by an address, comprising: at least two delay means, each delay means setting a different delay time period from said clock and delaying said clock; selecting means for receiving signals generated from said delay means and selecting one of said signals by a given control signal; and a data output buffer for receiving the data generated from said sense amplifier in response a signal generated from said selecting means and a latency information signal.
Claim 11
Dependent Claim
32 words
The semiconductor memory device as claimed in claim 7, wherein said data output buffer further includes a latch circuit for temporarily storing data received by a signal generated from said selecting means.
References Cited (Backward Citations)
US4661928A
Cited
US4663741A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-23 | 1998-07-25 | 1999-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-23 | 2002-07-25 | 2003-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-23 | 2006-07-25 | 2007-01-24 | $7700.00 | Window Closed / Lapsed |