Patent US6914800B2 successfully refreshed from Google Patents.
US6914800B2
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Structures, methods, and systems for ferroelectric memory transistors
Assignee: Micron Technology Inc
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Filing: 2004-08-31
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Granted: 2005-07-05
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Expires: 2024-08-31
Abstract
Abstract Integrated memory circuits, key components in thousands of electronic and computer products, have recently been made using ferroelectric memory transistors, which offer faster write cycles and lower power requirements than over conventional floating-gate transistors. One problem that hinders the continued down-scaling of conventional ferroelectric memory transistors is the vulnerability of their gate insulations to failure at thinner dimensions. Accordingly, the inventors devised unique ferroelectric gate structures, one of which includes a high-integrity silicon-oxide insulative layer, a doped titanium-oxide layer, a weak-ferroelectric layer, and a control gate. The doped titanium-oxide layer replaces a metal layer in the conventional ferroelectric gate structure, and the weak-ferroelectric layer replaces a conventional ferroelectric layer. These replacements reduce the permittivity mismatch found in conventional gate structures, and thus reduce stress on gate insulation layers, thereby improving reliability of ferroelectric memory transistors, particularly those with thinner gate insulation.
Inventors
- 👤 Kie Y. Ahn
- 👤 Leonard Forbes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:09
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/689; H10D30/00; H10D30/60; H10D30/701; H10D64/01; H10D64/031; H10D64/033; H10B; H10B53/00
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
78 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 2
Independent Claim
78 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 3
Dependent Claim
17 words
The system of claim 1 , wherein the ferroelectric layer has a dielectric constant less than 1000.
Claim 4
Dependent Claim
29 words
The system of claim 2 , wherein the ferroelectric layer is characterized by a spontaneous polarization in a range of approximately 0.01 micro-Coulomb/cm 2 to 1 micro-Coulomb/cm 2 .
Claim 5
Dependent Claim
28 words
The system of claim 2 , wherein the doped insulative layer has a dielectric constant between that of the first insulative layer and that of the ferroelectric layer.
Claim 6
Dependent Claim
17 words
The system of claim 2 , wherein the first insulative layer consists essentially of a silicon oxide.
Claim 7
Dependent Claim
21 words
The system of claim 2 , wherein the doped insulative layer comprises at least one of strontium- or barium-doped titanium oxide.
Claim 8
Dependent Claim
35 words
The system of claim 2 , wherein the ferroelectric layer consists essentially of zinc oxide doped with magnesium at a level of about 1 mol percent to about 30 mol percent of the metal component.
Claim 9
Independent Claim
96 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization within a range of approximately 0.01 micro-Coulomb/cm 2 to 1 micro-Coulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 10
Independent Claim
96 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer characterized by a spontaneous polarization within a range of approximately 0.01 micro-Coulomb/cm 2 to 1 micro-Coulomb/cm 2 ; and a doped insulative layer between the first insulative layer and the ferroelectric layer.
Claim 11
Dependent Claim
28 words
The system of claim 8 , wherein the doped insulative layer has a dielectric constant between that of the first insulative layer and that of the ferroelectric layer.
Claim 12
Dependent Claim
17 words
The system of claim 8 , wherein the first insulative layer consists essentially of a silicon oxide.
Claim 13
Dependent Claim
21 words
The system of claim 8 , wherein the doped insulative layer comprises at least one of strontium- or barium-doped titanium oxide.
Claim 14
Independent Claim
87 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the ferroelectric layer is a weak ferroelectric layer.
Claim 15
Independent Claim
87 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the ferroelectric layer is a weak ferroelectric layer.
Claim 16
Dependent Claim
31 words
The system of claim 12 , wherein the ferroelectric layer is characterized by a spontaneous polarization within a range of approximately 0.01 micro Coulomb/cm 2 to 1 micro Coulomb/cm 2 .
Claim 17
Independent Claim
89 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the ferroelectric layer has a dielectric constant less than 1000.
Claim 18
Independent Claim
89 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the ferroelectric layer has a dielectric constant less than 1000.
Claim 19
Independent Claim
114 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the first insulative layer has a dielectric constant of about 4, the doped insulative layer has a dielectric constant of about 165 or 180, and the ferroelectric layer has a dielectric constant of about 250.
Claim 20
Independent Claim
114 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the first insulative layer has a dielectric constant of about 4, the doped insulative layer has a dielectric constant of about 165 or 180, and the ferroelectric layer has a dielectric constant of about 250.
Claim 21
Independent Claim
107 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the ferroelectric layer consists essentially of zinc oxide doped with lithium at a level of about 1 mol percent to about 30 mol percent of the metal component.
Claim 22
Independent Claim
107 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a drain region and a source region; and a stacked gate structure including: a first insulative layer on the silicon substrate between the drain and source regions; a ferroelectric layer; and a doped insulative layer between the first insulative layer and the ferroelectric layer, wherein the ferroelectric layer consists essentially of zinc oxide doped with lithium at a level of about 1 mol percent to about 30 mol percent of the metal component.
Claim 23
Independent Claim
80 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a strontium doped titanium oxide layer on the silicon oxide layer; a doped zinc oxide layer on the doped titanium oxide layer; and a gate conductor on the zinc oxide layer.
Claim 24
Independent Claim
80 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a strontium doped titanium oxide layer on the silicon oxide layer; a doped zinc oxide layer on the doped titanium oxide layer; and a gate conductor on the zinc oxide layer.
Claim 25
Independent Claim
83 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a strontium doped titanium oxide layer on the silicon oxide layer; a lithium doped zinc oxide layer on the doped titanium oxide layer; and a gate conductor on the lithium doped zinc oxide layer.
Claim 26
Independent Claim
83 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a strontium doped titanium oxide layer on the silicon oxide layer; a lithium doped zinc oxide layer on the doped titanium oxide layer; and a gate conductor on the lithium doped zinc oxide layer.
Claim 27
Independent Claim
83 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a strontium doped titanium oxide layer on the silicon oxide layer; a magnesium doped zinc oxide layer on the doped titanium oxide layer; and a gate conductor on the magnesium doped zinc oxide layer.
Claim 28
Independent Claim
83 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a strontium doped titanium oxide layer on the silicon oxide layer; a magnesium doped zinc oxide layer on the doped titanium oxide layer; and a gate conductor on the magnesium doped zinc oxide layer.
Claim 29
Independent Claim
81 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a barium doped titanium oxide layer on the silicon oxide layer; a doped zinc oxide layer on the barium doped titanium oxide layer; and a gate conductor on the zinc oxide layer.
Claim 30
Independent Claim
81 words
A system comprising: at least one processor; and a memory device coupled to the processor, wherein the memory device comprises a plurality of ferroelectric memory transistors, with each transistor comprising: a silicon substrate having a desired channel conduction region; a silicon oxide layer over the desired channel conduction region; a barium doped titanium oxide layer on the silicon oxide layer; a doped zinc oxide layer on the barium doped titanium oxide layer; and a gate conductor on the zinc oxide layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2008-07-04 | 2009-01-03 | 2009-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2012-07-04 | 2013-01-03 | 2013-07-05 | $3760.00 | Window Closed / Lapsed |
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