US5847989A
Expired / Lapsed
US
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Ferroelectric memory using non-remnant reference circuit
Assignee: Micron Technology Inc
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Filing: 1997-09-02
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Granted: 1998-12-08
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Expires: 2017-09-02
Abstract
Abstract A random access memory circuit uses single ferroelectric memory cells to store data. The ferroelectric memory cells can be selectively read using a reference voltage which is compared to a voltage representative of data stored on the memory cell using a multiplexed sense amplifier. The reference voltage is generated using a non-remnant capacitor circuit coupled to a bit line. In using a non-remnant capacitor circuit, a single-ended reference voltage can be generated on the bit line. The capacitance of the bit line is substantially greater than the capacitance of the non-remnant capacitor, therefore, the resultant reference voltage on the bit line remains relatively constant with fluctuations in supply voltage. A ferroelectric memory cell can then be read by comparing the voltage on its corresponding bit line to the reference voltage using the sense amplifier.
Inventors
- 👤 Mirmajid Seyyedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/22
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
66 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage.
Claim 2
Dependent Claim
66 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage.
Claim 3
Dependent Claim
42 words
The integrated circuit memory of claim 1 wherein the reference circuitry comprises: a voltage regulator connected to a supply voltage and selectively coupled to the non-remnant capacitor circuit; and isolation circuitry located electrically between the non-remnant capacitor circuit and the sense amplifier.
Claim 4
Dependent Claim
35 words
The integrated circuit memory of claim 2 further including a coupling transistor connected to the non-remnant capacitor circuit and the second bit line for selectively coupling the non-remnant capacitor circuit to the second bit line.
Claim 5
Dependent Claim
32 words
The integrated circuit memory of claim 2 further including a coupling transistor connected to the voltage regulator and the non-remnant capacitor circuit for selectively coupling the voltage regulator the non-remnant capacitor circuit.
Claim 6
Dependent Claim
80 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, a capacitance of the non-remnant capacitor circuit can be adjusted using an electronic key.
Claim 7
Dependent Claim
80 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, a capacitance of the non-remnant capacitor circuit can be adjusted using an electronic key.
Claim 8
Dependent Claim
28 words
The integrated circuit memory of claim 5 wherein the reference circuitry comprises a voltage regulator connected to a supply voltage and selectively coupled to the non-remnant capacitor circuit.
Claim 9
Independent Claim
105 words
A method of reading a ferroelectric memory comprising a plurality of ferroelectric memory cells, first and second bit lines, and a sense amplifier, the method comprising the steps of: equilibrating the first and second bit lines to a ground potential; selectively coupling one of the ferroelectric memory cells to the sense amplifier via the first bit line; raising a voltage of a plate line of the one of the ferroelectric memory cells to extract data stored in the ferroelectric memory cells; producing a positive reference voltage using a non-remnant capacitor; and electrically coupling the reference voltage to the sense amplifier via the second bit line.
Claim 10
Independent Claim
105 words
A method of reading a ferroelectric memory comprising a plurality of ferroelectric memory cells, first and second bit lines, and a sense amplifier, the method comprising the steps of: equilibrating the first and second bit lines to a ground potential; selectively coupling one of the ferroelectric memory cells to the sense amplifier via the first bit line; raising a voltage of a plate line of the one of the ferroelectric memory cells to extract data stored in the ferroelectric memory cells; producing a positive reference voltage using a non-remnant capacitor; and electrically coupling the reference voltage to the sense amplifier via the second bit line.
Claim 11
Dependent Claim
57 words
The method of claim 7 wherein the step of producing the reference voltage comprises the steps of: charging the non-remnant capacitor to a pre-determined positive voltage; and sharing the charge stored on the non-remnant capacitor with the second bit line, where a capacitance of the second bit line is greater than the capacitance of the non-remnant capacitor.
Claim 12
Dependent Claim
119 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, the non-remnant capacitor circuit is comprised of a conductor line having a line capacitance, and a plurality of capacitors selectively coupled to the conductor line via access devices, wherein a capacitance of each of the first and second bit lines is an order of magnitude greater than a capacitance of the reference circuitry.
Claim 13
Dependent Claim
119 words
An integrated circuit memory comprising: an array of ferroelectric memory cells; a sense amplifier to sense and amplify data stored on the ferroelectric memory cells; first and second bit lines for coupling the ferroelectric memory cells to the sense amplifier; and reference circuitry selectively coupled to either the first or second bit line, the reference circuitry having a non-remnant capacitor circuit for providing a reference voltage, the non-remnant capacitor circuit is comprised of a conductor line having a line capacitance, and a plurality of capacitors selectively coupled to the conductor line via access devices, wherein a capacitance of each of the first and second bit lines is an order of magnitude greater than a capacitance of the reference circuitry.
Claim 14
Dependent Claim
28 words
The integrated circuit memory of claim 9 wherein the reference circuitry comprises a voltage regulator connected to a supply voltage and selectively coupled to the non-remnant capacitor circuit.
Claim 15
Dependent Claim
141 words
An integrated circuit memory comprising: a sense amplifier having first and second sensing nodes; a first pair of bit lines connected to the first and second sensing nodes of the sense amplifier; a second pair of bit lines connected to the first and second sensing nodes of the sense amplifier; ferroelectric memory cells coupled to the first and second pair of bit lines; a reference line having a capacitance; a plurality of capacitors coupled to the reference line through access transistors; and isolation devices connected to the reference line and the second pair of bit lines for coupling the reference line to either the first or second reference node of the sense amplifier via the second pair of bit lines, wherein a capacitance of a bit line is an order of magnitude greater than a capacitance of the plurality of capacitors.
Claim 16
Dependent Claim
141 words
An integrated circuit memory comprising: a sense amplifier having first and second sensing nodes; a first pair of bit lines connected to the first and second sensing nodes of the sense amplifier; a second pair of bit lines connected to the first and second sensing nodes of the sense amplifier; ferroelectric memory cells coupled to the first and second pair of bit lines; a reference line having a capacitance; a plurality of capacitors coupled to the reference line through access transistors; and isolation devices connected to the reference line and the second pair of bit lines for coupling the reference line to either the first or second reference node of the sense amplifier via the second pair of bit lines, wherein a capacitance of a bit line is an order of magnitude greater than a capacitance of the plurality of capacitors.
Claim 17
Dependent Claim
24 words
The integrated circuit memory of claim 11 further comprising a voltage regulator connected to a supply voltage and selectively coupled to the reference line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-12-07 | 2002-06-08 | 2002-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-12-07 | 2006-06-08 | 2006-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-12-07 | 2010-06-08 | 2010-12-08 | $7700.00 | Window Closed / Lapsed |