Dynamic adjusting reference voltage for ferroelectric circuits

Claim 2

A reference circuit for generating a reference voltage for use with ferroelectric memory circuits, comprising: a first and second sense capacitances; a first ferroelectric capacitor and a first select transistor connected so that when selected by a signal, said first ferroelectric capacitor is connected in series with said first sense capacitance; a second ferroelectric capacitor and a second select transistor connected so that when selected by a signal, said second ferroelectric capacitor is connected in series with said second sense capacitance; and a circuit for short circuiting a junction between said first ferroelectric capacitor and said first sense capacitance to a junction between said second ferroelectric capacitor and said second sense capacitance, a voltage at said short circuited junction defining said reference voltage.

Claim 3

The reference circuit of claim 1, wherein said select transistors comprise field effect transistors, each having a gate terminal connected together for simultaneous selection.

Claim 4

The reference circuit of claim 1, further including a pair of bit lines, each bit line connected to a different said ferroelectric capacitor via a respective said select transistor.

Claim 5

The reference circuit of claim 1, wherein each said ferroelectric capacitor includes spaced-apart plates with a ferroelectric material therebetween, and wherein one said plate of each said ferroelectric capacitor is connected together.

Claim 6

The reference circuit of claim 1, wherein said circuit for short circuiting said junctions comprises at least one transistor.

Claim 7

The reference circuit of claim 1, wherein said circuit for short circuiting comprises a CMOS pass gate transistor pair.

Claim 8

The reference circuit of claim 1, further including means for writing each said ferroelectric capacitor with a different polarization state.

Claim 9

A reference circuit for use with a ferroelectric memory, comprising: a pair of sense capacitances; a complementary cell defined by a pair of select transistors and a ferroelectric capacitor associated with each said transistor, each said select transistor being effective to connect one said ferroelectric capacitor in series with one said sense capacitance so that an amount of electrical charge read from a respective ferroelectric capacitor is transferred to said sense capacitance in proportion to a polarization state stored in the respective ferroelectric capacitors; and a circuit for generating an average voltage of the voltage across the sense capacitances, said average voltage defining said reference voltage.

Claim 10

A reference circuit for use with a ferroelectric memory, comprising: a pair of sense capacitances; a complementary cell defined by a pair of select transistors and a ferroelectric capacitor associated with each said transistor, each said select transistor being effective to connect one said ferroelectric capacitor in series with one said sense capacitance so that an amount of electrical charge read from a respective ferroelectric capacitor is transferred to said sense capacitance in proportion to a polarization state stored in the respective ferroelectric capacitors; and a circuit for generating an average voltage of the voltage across the sense capacitances, said average voltage defining said reference voltage.

Claim 11

The reference circuit of claim 8, further including means for storing different polarization states in each said ferroelectric capacitor.

Claim 12

The reference circuit of claim 8, further including in combination a ferroelectric memory array comprising rows and columns of memory cells, and one said reference circuit for each addressable row.

Claim 15

The method of claim 11, further including carrying out the averaging step by short circuiting one plate of each said sense capacitance together.

Claim 16

The method of claim 11, further including restoring opposite polarization states in the respective ferroelectric capacitors after each said averaging step.

Claim 17

The method of claim 13, further including carrying out the restoring step by driving one plate of each said ferroelectric capacitor to opposite voltage states.

Claim 18

A ferroelectric memory, comprising: an array of ferroelectric memory cells, each cell having a single select transistor and a single ferroelectric capacitor connected between a drive line and a bit line by said select transistor, said array comprising plural rows and plural columns of said cells; a sense amplifier connected to each said bit line; for each row of cells of said array, an associated reference cell defined by a pair of select transistors and a pair of ferroelectric capacitors polarizable in opposite states, each said ferroelectric capacitor of each said reference cell being connectable to a different bit line of the reference cell, wherein when each row of the array of ferroelectric memory cells is accessed, a corresponding reference cell is also accessed; a sense capacitance associated with each bit line of each reference cell; means for short circuiting together the bit lines of each reference cell to obtain an average voltage developed across the sense capacitances; and a conductor for coupling the average voltage to each said sense amplifier.

Claim 19

A ferroelectric memory, comprising: an array of ferroelectric memory cells, each cell having a single select transistor and a single ferroelectric capacitor connected between a drive line and a bit line by said select transistor, said array comprising plural rows and plural columns of said cells; a sense amplifier connected to each said bit line; for each row of cells of said array, an associated reference cell defined by a pair of select transistors and a pair of ferroelectric capacitors polarizable in opposite states, each said ferroelectric capacitor of each said reference cell being connectable to a different bit line of the reference cell, wherein when each row of the array of ferroelectric memory cells is accessed, a corresponding reference cell is also accessed; a sense capacitance associated with each bit line of each reference cell; means for short circuiting together the bit lines of each reference cell to obtain an average voltage developed across the sense capacitances; and a conductor for coupling the average voltage to each said sense amplifier.

Claim 20

The ferroelectric memory of claim 15, wherein each row of the memory array has multiple bits that are read during an access cycle.

Claim 21

The ferroelectric memory of claim 15, further including means for polarizing the ferroelectric capacitors of each said reference cell to opposite states.

Claim 22

The ferroelectric memory of claim 15, wherein each reference cell is connected in common to a pair of bit lines.

Claim 23

The ferroelectric memory of claim 15, further including a memory word line connected to a row of select transistors of the memory array and connected to the select transistors of a reference cell, and a drive line connected in common to memory cells of the array and to at least one reference cell.

Claim 26

The method of claim 20, wherein said memory comprises multiple row and columns of said memory cells, and further including discharging different said first and second reference ferroelectric capacitors for each row of cells accessed to develop a respective reference voltage for each said row of memory cells.

Claim 27

The method of claim 20, further including restoring opposite polarization states in each said first and second reference ferroelectric capacitors after each said accessing step.

Claim 28

The method of claim 20, further including carrying out the averaging step by short circuiting the first and second voltages together.

Claim 31

The method of claim 24, further including simultaneously polarizing different said ferroelectric capacitors, each with a different polarization state.

Claim 32

The method of claim 24, further including sequentially polarizing one ferroelectric capacitor to one polarization state and thereafter polarizing the other ferroelectric capacitor to the different polarization state.

Claim 33

The method of claim 24, wherein said deriving step is carried out by short circuiting the representative voltages together to achieve said average voltage.

Claim 34

The method of claim 24, further including discharging the ferroelectric capacitor with the one polarization state to a first series-connected capacitor, and discharging the ferroelectric capacitor with the different polarization state to a second series-connected capacitor.

Claim 35

The method of claim 28, further including shorting a plate of each said series-connected capacitor together to derive the average of the representative voltages.

Claim 36

The method of claim 29, further including shorting the series-connected capacitors by driving a transistor connected to each said series-connected capacitor into conduction.