Ferroelectric memory cell and method of sensing and writing the polarization state thereof

Claim 3

A method of sensing the polarization state of a ferroelectric memory cell as claimed in claim 1 wherein the step of storing a reference charge in the reference capacitor includes the steps of determining approximately the largest second amount of charge flow that can occur, determining the largest errors that can occur in the comparing step and setting the stored reference charge greater than the combination of the determined largest second amount and the largest errors.

Claim 4

A method of sensing the polarization state of a ferroelectric memory cell as claimed in claim 1 wherein the step of providing a reference cell with a reference capacitor includes providing a reference cell with one of a ferroelectric capacitor and a linear capacitor.

Claim 5

A ferroelectric memory cell and associated reference cell comprising: a ferroelectric memory cell including a switching device and a ferroelectric capacitor with first and second terminals, the ferroelectric capacitor having a hysterisis curve with upper and lower electric field points and upper and lower permanent remnant polarization points the upper and lower permanent remnant polarization points being stable operating points; a reference cell having a switching circuit and a reference capacitor; a sense amplifier having an activating input terminal and a pair of differentially connected output terminals; first and second bit lines connected to the differentially connected output terminals of the sense amplifier, the switching device of the ferroelectric memory cell connecting the first terminal of the ferroelectric capacitor to the first bit line when activated and the switching circuit of the reference cell connecting the reference capacitor to the second bit line when activated; and an electric potential input line attached to the second terminal of the memory cell for cycling the ferroelectric capacitor between substantially zero electric potential thereacross, an electric potential sufficient to move the polarization to one of the upper and lower electric field points and back to substantially zero electric potential such that upon sequentially activating the switching device and switching circuit, applying an electric potential to the electric potential line to activate the sense amplifier, removing the electric potential to move the polarization of the ferroelectric capacitor back to substantially zero electric potential and deactivating the sense amplifier the ferroelectric cell is sensed and refreshed.

Claim 6

A ferroelectric memory cell and associated reference cell comprising: a ferroelectric memory cell including a switching device and a ferroelectric capacitor with first and second terminals, the ferroelectric capacitor having a hysterisis curve with upper and lower electric field points and upper and lower permanent remnant polarization points the upper and lower permanent remnant polarization points being stable operating points; a reference cell having a switching circuit and a reference capacitor; a sense amplifier having an activating input terminal and a pair of differentially connected output terminals; first and second bit lines connected to the differentially connected output terminals of the sense amplifier, the switching device of the ferroelectric memory cell connecting the first terminal of the ferroelectric capacitor to the first bit line when activated and the switching circuit of the reference cell connecting the reference capacitor to the second bit line when activated; and an electric potential input line attached to the second terminal of the memory cell for cycling the ferroelectric capacitor between substantially zero electric potential thereacross, an electric potential sufficient to move the polarization to one of the upper and lower electric field points and back to substantially zero electric potential such that upon sequentially activating the switching device and switching circuit, applying an electric potential to the electric potential line to activate the sense amplifier, removing the electric potential to move the polarization of the ferroelectric capacitor back to substantially zero electric potential and deactivating the sense amplifier the ferroelectric cell is sensed and refreshed.

Claim 7

A ferroelectric memory cell and associated reference cell as claimed in claim 4 wherein the electric potential input line attached to the memory cell for cycling the ferroelectric capacitor is designed to receive an electric potential which cycles the ferroelectric capacitor between substantially zero electric potential, an electric potential sufficient to move the polarization to the upper electric field point and back to substantially zero electric potential.

Claim 8

A ferroelectric memory cell and associated reference cell as claimed in claim 4 wherein the electric potential input line attached to the memory cell for cycling the ferroelectric capacitor is designed to receive an electric potential which cycles the ferroelectric capacitor between substantially zero electric potential, an electric potential sufficient to move the polarization to the lower electric field point and back to substantially zero electric potential.

Claim 9

A ferroelectric memory cell and associated reference cell as claimed in claim 4 wherein the reference capacitor is designed to provide an electric charge which is equal to a largest postulated polarization change of the ferroelectric capacitor plus a margin for worst case imbalance of the means for comparing.

Claim 10

A ferroelectric memory cell and associated reference cell as claimed in claim 4 wherein the reference capacitor includes one of a ferroelectric capacitor and a linear capacitor.