EP0364813B1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device with memory cells including ferroelectric capacitors
Assignee: Toshiba Corp
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Filing: 1989-10-04
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Granted: 1994-03-23
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Expires: 2009-10-04
Abstract
No abstract record available.
Inventors
- 👤 Haruki Intellectual Property Division Toda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 18:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/22
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
226 words
A semiconductor memory device including bit line pairs including first and second bit lines (BL, BL ) to be set at a first logic level corresponding to data "1" or a second logic level corresponding to data "0", a first memory cell (MC1) coupled with said first bit line (BL) of said bit line pairs (BL, BL ), said first memory cell containing a first ferroelectric capacitor (C1) with first and second electrode plates, and a first transistor (T1) connected between said first electrode plate of said first ferroelectric capacitor (C1) and said first bit line (BL), said first transistor (T1) transferring data therebetween; plate potential setting means (90) for setting a potential (VPF) at said second electrode plate of said first ferroelectric capacitor (C1), characterized in that said potential at said second plate is set at a mid value between said first and second logic levels; and a distance D between said first and second electrode plates of said first ferroelectric capacitor (C1) being selected such that a minimum voltage Et × D to saturate an intensity of the polarization of said first ferroelectric capacitor (C1) is smaller than a value amounting to substantially half of the difference between said first and second logic levels, where Et indicates a field strength enough to saturate the intensity of the polarization of said first ferroelectric capacitor (C1).
Claim 2
Dependent Claim
115 words
The semiconductor memory device according to claim 1, characterized in that said first transistor (T1) includes a source region (5) and a drain region (5') which are separately formed on a semiconductor substrate (1), and a gate electrode (4) formed on an insulating layer (3) laid on said substrate (1), and said first ferroelectric capacitor (C1) includes a first conductive layer (7) serving as said first electrode plate and being formed on said substrate (1) so as to be coupled with said source region (5), a ferroelectric layer (8) formed on said first conductive layer (7), and a second conductive layer (9) formed on said ferroelectric layer (8) and serving as said second electrode plate.
Claim 3
Dependent Claim
131 words
The semiconductor memory device according to claim 1, characterized by further comprising a reference potential generating means (REF1) such that when said first memory cell (MC1) is selected, said reference potential generating means sets said second bit line ( BL ) at a predetermined reference potential, and sense amplifying means for amplifying a potential difference between said first bit line (BL) to be set at a potential in accordance with data read out of said first memory cell (MC1) and said second bit line ( BL ) to be set at said reference potential by said reference potential generating means (REF1), said sense amplifying means (SA1) setting one of said first and second bit lines (BL, BL ) in said first logic level and the other in said second logic level.
Claim 4
Dependent Claim
74 words
The semiconductor memory device according to claim 3, characterized in that said reference potential generated by said reference potential generating means (REF1) is a mid potential between the potential of said first bit line (BL) as set in accordance with data "1" read out of said first memory cell (MC1) and the potential of said first bit line (BL) as set in accordance with data "0" read out of said first memory cell (MC1).
Claim 5
Dependent Claim
89 words
The semiconductor memory device according to claim 3, characterized in that said reference potential generating means (REF1) includes a reference cell ( RC ) coupled with said second bit line ( BL ), and said reference cell ( RC ) includes first and second ferroelectric capacitors (DC1, DC2) each having first and second electrode plates, and data transfer means (DT1, DT2) being connected between said first electrode plates of said first and second ferroelectric capacitors (DC1, DC2) and said second bit line ( BL ), and transferring data therebetween.
Claim 6
Dependent Claim
50 words
The semiconductor memory device according to claim 5, characterized in that the capacitance C and electrode plate area A of each said first and second ferroelectric capacitors (DC1, DC2) of said reference cell ( RC ) are half those of said ferroelectric capacitor (C1) of said first memory cell (MC1).
Claim 7
Dependent Claim
103 words
The semiconductor memory device according to claim 5, characterized in that said second electrode plate of said first ferroelectric capacitor (DC1) of said reference cell ( RC ) is connected to either of the power source potential supply terminal for supplying said first logic level or the ground potential supply terminal for supplying said second logic level, and said second electrode plate of said second ferroelectric capacitor (DC2) of said reference cell ( RC ) is connected to the output of said plate potential setting means (90) so as to be set at a mid potential between said first and second logic levels.
Claim 8
Dependent Claim
120 words
The semiconductor memory device according to claim 5, characterized in that said reference potential generating means (90) further includes bit line potential setting means (LS1, Vss) for setting said first and second bit lines (BL, BL ) at said second logic level before said second bit line ( BL ) is set at said reference potential, and reference data write means (DS1, Vcc) for writing reference data into said second ferroelectric capacitor (DC2) of said reference cell ( RC ) so that the polarity of an electric field retained in said second ferroelectric capacitor (DC2) of said reference cell ( RC ) is reversed by the potential of said second logic level on said second bit line ( BL ).
Claim 9
Dependent Claim
155 words
The semiconductor memory device according to claim 5, characterized by further comprising precharge means (PR1) for precharging said first and second bit lines (BL, BL ) at a mid potential between said first and second logic levels, plate potential detecting means (91) for detecting the potential of said second electrode plate of said first ferroelectric capacitor (C1) of said first memory cell (MC1), and access control means (93, 96, 97) allowing access to said first memory cell (MC1) when said bit line potential detecting means (92) detects a state wherein said first and second bit lines (BL, BL ) are precharged to a potential midway between said first and second logic levels, and said plate potential detecting means (91) detects a state wherein the potential of said second electrode plate of said first ferroelectric capacitor (C1) of said first memory cell (MC1) is set at a potential midway between said first and second logic levels.
Claim 10
Dependent Claim
197 words
The semiconductor memory device according to claim 1, characterized by further comprising a second memory cell (MC2) coupled with said second bit line ( BL ) of said bit line pairs (BL, BL ), said second memory cell (MC2) containing a second ferroelectric capacitor (C2) with first and second electrode plates, and a second transistor (T2) connected between said first electrode plate of said second ferroelectric capacitor (C2) and said second bit line ( BL ), said second transistor (T2) transferring data therebetween, and in which the potential at said second electrode plate of said second ferroelectric capacitor (C2) is set at a mid value between said first and second logic levels by said plate potential setting means (90), and a distance D between said first and second electrode plates of said second ferroelectric capacitor (C2) is selected such that a minimum voltage Et × D to saturate the intensity of the polarization of said second ferroelectric capacitor (C2) is smaller than a value amounting to substantially half the difference between said first and second logic levels, where Et indicates a field strength enough to the intensity of the saturate polarization of said second ferroelectric capacitor (C2).
Claim 11
Dependent Claim
123 words
The semiconductor memory device according to claim 10, characterized by further comprising a reference potential generating means (REF1) such that when said first memory cell (MC1) is selected, said reference potential generating means (FEF1) sets said second bit line ( BL ) at a predetermined reference potential, and when said second memory cell (MC2) is selected, said reference potential generating means (REF1) sets said first bit line (BL) at said predetermined reference potential, and sense amplifying means (SA1) for amplifying a potential difference between said first and second bit lines (BL, BL ), said sense amplifying means (SA1) setting one of said first and second bit lines (BL, BL ) in said first logic level and the other in said second logic level.
References Cited (Backward Citations)
No citation records indexed.
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