Method of fabricating a field effect transistor structure with abrupt source/drain junctions

Abstract

Abstract Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer ( 108 ) adjacent to the vertical sidewalls of the gate electrode ( 106 ), or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.

Inventors

• 👤 Anand S. Murthy
• 👤 Robert S. Chau
• 👤 Patrick Morrow
• 👤 Chia-Hong Jan
• 👤 Paul Packan

Bibliographic Details