US5300447A
Expired / Lapsed
US
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Method of manufacturing a minimum scaled transistor
Assignee: Texas Instruments Inc
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Filing: 1992-09-29
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Granted: 1994-04-05
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Expires: 2012-09-29
Abstract
Abstract An extremely small minimum scaled Metal-Oxide-Semiconductor, MOS, transistor is manufactured by forming a trench in a semiconductor substrate, forming a gate in the trench, and then forming source and drain regions. The source and drain regions may be diffused into the semiconductor substrate and annealed to drive the diffusions around the trench corners, thus forming the transistor channel. This improves punchthrough resistance of the transistor while yielding an extremely small gate channel. The diffusion concentration will be larger near the surface of the semiconductor substrate and smaller near the plane of the gate channel underneath the trench bottom. The trench corners have the effect of serving as a line source of dopant for diffusion under the trench such that the doping profile is the same along a radius of a cylindrical junction, thus keeping the minimum diffusion separation at the channel surface.
Inventors
- 👤 Dirk N. Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:37
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/025; H10D64/027
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
74 words
A method of fabricating a transistor, comprising the steps of: forming a trench in a face of semiconductor material of a conductivity type, the trench having sidewalls and having a bottom with corners; forming a dielectric layer in the trench; forming a conductor layer in the trench; doping areas on sides of the trench to an opposite conductivity type; and driving the opposite doped areas on sides of the trench around the trench corners.
Claim 2
Independent Claim
74 words
A method of fabricating a transistor, comprising the steps of: forming a trench in a face of semiconductor material of a conductivity type, the trench having sidewalls and having a bottom with corners; forming a dielectric layer in the trench; forming a conductor layer in the trench; doping areas on sides of the trench to an opposite conductivity type; and driving the opposite doped areas on sides of the trench around the trench corners.
Claim 3
Dependent Claim
82 words
The method of claim 1 wherein the step of forming the dielectric layer in the trench comprises the steps of: forming a dielectric layer on the trench bottom; forming a dielectric layer on the trench sidewalls, the dielectric layer on the trench sidewalls having a width; and wherein the step of driving the opposite doped areas on sides of the trench around the trench corners includes driving below the trench bottom to about the width of the dielectric on the trench walls.
Claim 4
Dependent Claim
13 words
The method of claim 2 wherein the driving step is performed by annealing.
Claim 5
Independent Claim
73 words
A method of fabricating a transistor, comprising the steps of: forming a trench in the surface of a semiconductor substrate, the trench having a bottom; forming a gate insulator layer in the trench; forming a gate conductor layer in the trench; and forming a transistor channel plane below the trench by providing source/drain diffusions in the surface of the semiconductor substrate that extend below the trench bottom and have a space between them.
Claim 6
Independent Claim
73 words
A method of fabricating a transistor, comprising the steps of: forming a trench in the surface of a semiconductor substrate, the trench having a bottom; forming a gate insulator layer in the trench; forming a gate conductor layer in the trench; and forming a transistor channel plane below the trench by providing source/drain diffusions in the surface of the semiconductor substrate that extend below the trench bottom and have a space between them.
Claim 7
Dependent Claim
24 words
The method of claim 4 wherein the source/drain diffusions have higher dopant concentrations above the transistor channel plane than below the transistor channel plane.
Claim 8
Dependent Claim
49 words
The method of claim 5 wherein the step of forming the transistor channel plane occurs by diffusing source/drain dopant material into the semiconductor substrate and annealing the dopant material so that it diffuses down into the substrate about as deep as the trench and around the trench bottom corners.
Claim 9
Independent Claim
116 words
A method of making a self aligned recessed channel MOS transistor, comprising the steps of: forming a recess in a face of a semiconductor wafer, the recess having a bottom; forming sidewall insulators in the recess; forming a thin gate dielectric in the recess; forming a transistor gate in the recess between the sidewall insulators; forming transistor source and drain diffusions in the face of the semiconductor wafer on sides of the recess; and annealing the source and drain diffusions, the annealing causing the source and drain diffusions to outdiffuse around the bottom of the recess, thereby creating a transistor channel below the bottom of the recess, self aligned to the transistor gate within the trench.
Claim 10
Independent Claim
116 words
A method of making a self aligned recessed channel MOS transistor, comprising the steps of: forming a recess in a face of a semiconductor wafer, the recess having a bottom; forming sidewall insulators in the recess; forming a thin gate dielectric in the recess; forming a transistor gate in the recess between the sidewall insulators; forming transistor source and drain diffusions in the face of the semiconductor wafer on sides of the recess; and annealing the source and drain diffusions, the annealing causing the source and drain diffusions to outdiffuse around the bottom of the recess, thereby creating a transistor channel below the bottom of the recess, self aligned to the transistor gate within the trench.
Claim 11
Dependent Claim
37 words
The method of claim 7 wherein the step of annealing the source and drain diffusions provides a higher dopant concentration level near the semiconductor surface and a lower dopant concentration level around the bottom of the recess.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |