Method of forming complementary device structures in partially processed dielectrically isolated wafers

Claim 1

A method of forming semiconductor wafer structures including dielectrically isolated tub regions of differing resistivities, the method comprising the steps of: (a) providing a plurality of silicon tubs, exhibiting a first resistivity value, in a semiconductor substrate, each tub including a layer of dielectric material covering the side and bottom surfaces thereof; (b) forming a patterning layer over the top major surface of said substrate; (c) opening windows of predetermined widths in said patterning layer over tubs selected to be of a second, different, resistivity value, with selected windows being formed to comprise a width w less than the width of the associated tub region; (d) removing the silicon material from the exposed tubs as determined by the predetermined window widths, wherein the selected windows with width w allowing a portion of the silicon tub material to remain in the exposed tubs at the end of the removal step; (e) ion implanting the remaining silicon tub material portions in said selected tubs of step d), said implantation of a predetermined resistivity value so as to form a wrap-around layer over the dielectric isolation layer; and (f) growing an epitaxial silicon layer exhibiting the second resistivity value in the areas exposed in step (d).

Claim 2

A method of forming semiconductor wafer structures including dielectrically isolated tub regions of differing resistivities, the method comprising the steps of: (a) providing a plurality of silicon tubs, exhibiting a first resistivity value, in a semiconductor substrate, each tub including a layer of dielectric material covering the side and bottom surfaces thereof; (b) forming a patterning layer over the top major surface of said substrate; (c) opening windows of predetermined widths in said patterning layer over tubs selected to be of a second, different, resistivity value, with selected windows being formed to comprise a width w less than the width of the associated tub region; (d) removing the silicon material from the exposed tubs as determined by the predetermined window widths, wherein the selected windows with width w allowing a portion of the silicon tub material to remain in the exposed tubs at the end of the removal step; (e) ion implanting the remaining silicon tub material portions in said selected tubs of step d), said implantation of a predetermined resistivity value so as to form a wrap-around layer over the dielectric isolation layer; and (f) growing an epitaxial silicon layer exhibiting the second resistivity value in the areas exposed in step (d).