US6187620B1
Expired / Lapsed
US
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Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
Assignee: Advanced Micro Devices Inc
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Filing: 1998-11-10
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Granted: 2001-02-13
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Expires: 2018-11-10
Abstract
Abstract A method is provided for forming an integrated circuit having junctions of n-channel transistors dissimilar to junctions of p-channel transistors. First and second gate conductors are formed upon a gate dielectric on a semiconductor substrate. Spacers are formed on sidewalls of the first and second gate conductors. Portions of the spacers are subsequently removed such that the lateral width of each spacer is reduced to form residual spacers. The residual spacers may subsequently be removed, exposing sidewalls of the first and second gate conductors. At various stages of the method, n-type impurities may be implanted into the substrate, masked by the first gate conductor and any adjacent spacers or residual spacers. P-type impurites may also be implanted into the substrate, masked by the second gate conductor and any adjacent spacers or residual spacers. More n-type than p-type impurity implants are preferably used, so that n-type junction regions formed on either side of the first gate conductor have a more graded profile than do the p-type junction regions formed on either side of the second gate conductor.
Inventors
- 👤 H. Jim Fulford, Jr.
- 👤 Mark I. Gardner
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:07
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D30/00; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/015; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10D84/8312; H10D84/8316
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
137 words
A method for forming an integrated circuit, comprising: forming first and second gate conductors dielectrically spaced above a semiconductor substrate; forming spacers laterally adjacent sidewalls of the first and second gate conductors; reducing a lateral width of each of the spacers to form residual spacers adjacent sidewalls of the first and second gate conductors; implanting a p-type impurity distribution into the semiconductor substrate on either side of the second gate conductor to form p-type junction regions; and implanting multiple n-type impurity distributions into the semiconductor substrate on either side of the first gate conductor to form graded n-type junction regions, wherein said n-type junction regions comprise more implanted impurity distributions than do said p-type junction regions and wherein the last n-type impurity distribution into the semiconductor substrate is masked by the first gate conductor absent any spacers.
Claim 2
Independent Claim
137 words
A method for forming an integrated circuit, comprising: forming first and second gate conductors dielectrically spaced above a semiconductor substrate; forming spacers laterally adjacent sidewalls of the first and second gate conductors; reducing a lateral width of each of the spacers to form residual spacers adjacent sidewalls of the first and second gate conductors; implanting a p-type impurity distribution into the semiconductor substrate on either side of the second gate conductor to form p-type junction regions; and implanting multiple n-type impurity distributions into the semiconductor substrate on either side of the first gate conductor to form graded n-type junction regions, wherein said n-type junction regions comprise more implanted impurity distributions than do said p-type junction regions and wherein the last n-type impurity distribution into the semiconductor substrate is masked by the first gate conductor absent any spacers.
Claim 3
Dependent Claim
41 words
The method as recited in claim 1 , wherein said forming first and second gate conductors comprises forming polysilicon gate conductors and subsequently forming a dielectric on exposed surfaces of the polysilicon gate conductors such that dielectric-covered gate conductors are formed.
Claim 4
Dependent Claim
17 words
The method as recited in claim 1 , wherein said forming spacers comprises forming silicon nitride spacers.
Claim 5
Dependent Claim
16 words
The method as recited in claim 1 , wherein said forming spacers comprises forming polysilicon spacers.
Claim 6
Dependent Claim
17 words
The method as recited in claim 1 , wherein said reducing the lateral width comprises isotropic etching.
Claim 7
Dependent Claim
15 words
The method as recited in claim 5 , wherein said isotropic etching comprises wet etching.
Claim 8
Dependent Claim
25 words
The method as recited in claim 1 , wherein said reducing the lateral width comprises simultaneously reducing a lateral width of each of the spacers.
Claim 9
Dependent Claim
50 words
The method as recited in claim 7 , wherein said reducing the lateral width further comprises: removing a portion of each of the spacers to form first residual spacers; removing a portion of each of the first residual spacers to form second residual spacers; and removing the second residual spacers.
Claim 10
Dependent Claim
78 words
The method as recited in claim 8 , wherein said implanting a p-type impurity distribution is performed prior to said removing a portion of each of the spacers, such that the p-type impurity distribution is masked by the second gate conductor and the spacers, and further comprising implanting an additional p-type impurity distribution subsequent to said removing the second residual spacers, such that the additional p-type impurity distribution is masked by the second gate conductor absent any spacers.
Claim 11
Dependent Claim
151 words
The method as recited in claim 9 , wherein said implanting multiple n-type impurity distributions comprises: implanting a first n-type impurity distribution prior to said removing a portion of each of the spacers, such that the first n-type impurity distribution is masked by the first gate conductor and the spacers; implanting a second n-type impurity distribution prior to said removing a portion of each of the first residual spacers, such that the second n-type impurity distribution is masked by the first gate conductor and the first residual spacers; implanting a third n-type impurity distribution prior to said removing the second residual spacers, such that the third n-type impurity distribution is masked by the first gate conductor and the second residual spacers; and implanting a fourth n-type impurity distribution subsequent to said removing the second residual spacers, such that the fourth n-type impurity distribution is masked by only the first gate conductor.
Claim 12
Dependent Claim
44 words
The method as recited in claim 1 , wherein said implanting the p-type impurity distribution further comprises simultaneously covering the first gate conductor with a mask, and said implanting multiple n-type impurity distributions further comprises simultaneously covering the second gate conductor with a mask.
Claim 13
Independent Claim
162 words
A method for forming a transistor, comprising: forming first and second gate conductors dielectrically spaced above a semiconductor substrate; growing an oxide upon exposed surfaces of the first and second gate conductors to form first and second oxide-covered gate conductors; forming spacers laterally adjacent sidewalls of the first and second oxide-covered gate conductors, wherein the spacers comprise a material having dissimilar etching characteristics from the oxide; reducing a lateral width of each of the spacers to form residual spacers adjacent sidewalls of the first and second oxide-covered gate conductors, wherein said reducing a lateral width is performed on all of the spacers simultaneously and wherein the residual spacers comprise said material of the spacers; implanting a p-type impurity distribution into the semiconductor substrate on either side of the second oxide-covered gate conductor to form p-type junction regions; and implanting multiple n-type impurity distributions into the semiconductor substrate on either side of the first oxide-covered gate conductor to form graded n-type junction regions.
Claim 14
Independent Claim
162 words
A method for forming a transistor, comprising: forming first and second gate conductors dielectrically spaced above a semiconductor substrate; growing an oxide upon exposed surfaces of the first and second gate conductors to form first and second oxide-covered gate conductors; forming spacers laterally adjacent sidewalls of the first and second oxide-covered gate conductors, wherein the spacers comprise a material having dissimilar etching characteristics from the oxide; reducing a lateral width of each of the spacers to form residual spacers adjacent sidewalls of the first and second oxide-covered gate conductors, wherein said reducing a lateral width is performed on all of the spacers simultaneously and wherein the residual spacers comprise said material of the spacers; implanting a p-type impurity distribution into the semiconductor substrate on either side of the second oxide-covered gate conductor to form p-type junction regions; and implanting multiple n-type impurity distributions into the semiconductor substrate on either side of the first oxide-covered gate conductor to form graded n-type junction regions.
Claim 15
Dependent Claim
24 words
The method as recited in claim 12 , wherein said n-type junction regions comprise more implanted impurity distributions than do said p-type junction regions.
Claim 16
Dependent Claim
17 words
The method as recited in claim 12 , wherein said forming spacers comprises forming silicon nitride spacers.
Claim 17
Dependent Claim
16 words
The method as recited in claim 12 , wherein said forming spacers comprises forming polysilicon spacers.
Claim 18
Dependent Claim
17 words
The method as recited in claim 12 , wherein said reducing the lateral width comprises wet etching.
Claim 19
Dependent Claim
50 words
The method as recited in claim 12 , wherein said reducing the lateral width further comprises: removing a portion of each of the spacers to form first residual spacers; removing a portion of each of the first residual spacers to form second residual spacers; and removing the second residual spacers.
Claim 20
Dependent Claim
80 words
The method as recited in claim 17 , wherein said implanting a p-type impurity distribution is performed prior to said removing a portion of each of the spacers, such that the p-type impurity distribution is masked by the second oxide-covered gate conductor and the spacers, and further comprising implanting an additional p-type impurity distribution subsequent to said removing the second residual spacers, such that the additional p-type impurity distribution is masked by the second oxide-covered gate conductor absent any spacers.
Claim 21
Dependent Claim
155 words
The method as recited in claim 18 , wherein said implanting multiple n-type impurity distributions comprises: implanting a first n-type impurity distribution prior to said removing a portion of each of the spacers, such that the first n-type impurity distribution is masked by the first oxide-covered gate conductor and the spacers; implanting a second n-type impurity distribution prior to said removing a portion of each of the first residual spacers, such that the second n-type impurity distribution is masked by the first oxide-covered gate conductor and the first residual spacers; implanting a third n-type impurity distribution prior to said removing the second residual spacers, such that the third n-type impurity distribution is masked by the first oxide-covered gate conductor and the second residual spacers; and implanting a fourth n-type impurity distribution subsequent to said removing the second residual spacers, such that the fourth n-type impurity distribution is masked by only the first oxide-covered gate conductor.
Claim 22
Dependent Claim
44 words
The method as recited in claim 12 , wherein said implanting the p-type impurity distribution further comprises simultaneously covering the first gate conductor with a mask, and said implanting multiple n-type impurity distributions further comprises simultaneously covering the second gate conductor with a mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-13 | 2004-08-14 | 2005-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-13 | 2008-08-14 | 2009-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-13 | 2012-08-14 | 2013-02-13 | $7700.00 | Window Closed / Lapsed |