Fet device with double spacer

Claim 1

A FET device comprising: a substrate having a first type dopant; a gate insulating layer on the substrate; a polycrystalline silicon gate electrode on said gate insulating layer having vertical sidewalls; shallow impurity regions of a second opposite type dopant in said substrate that terminate adjacent the outside edges of said vertical sidewalls of said gate electrode; a layer of SiO 2 on the vertical sidewalls of said gate electrode; first spacers of polycrystalline silicon over said layer of SiO 2 on the gate electrode sidewalls; the top portion of the layer of SiO 2 on the gate electrode sidewalls being sufficiently conductive to keep the gate electrode and the first spacers of polycrystalline silicon at the same potential; second spacers of silicon oxide over said first spacers of polycrystalline silicon on the gate electrode sidewalls, the shallow impurity regions having a substantially constant first dopant concentration beneath the first spacers of polycrystalline silicon and the second spacers of silicon oxide; and source and drain regions of a second opposite type dopant in said substrate that terminate adjacent the edges of said second spacers, said source and drain regions extending deeper into said substrate than said shallow impurity regions and having a higher dopant concentration than the first dopant concentration.