US5493130A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers
Assignee: Micron Technology Inc
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Filing: 1994-04-28
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Granted: 1996-02-20
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Expires: 2014-04-28
Abstract
Abstract The disclosure pertains to a bottom and top gated thin film transistor and other circuitry constructions. In the thin film transistor construction, the top gate electrode (preferably polysilicon) overlaps with the channel region, and the top gate electrode has an electrically conductive sidewall (preferably oxide). The bottom gate electrode (preferably polysilicon) has an outer surface area which includes a portion which extends outwardly beyond the top gate electrode sidewall. An electrically conductive sidewall link overlies the electrically insulated channel region sidewall and extends between the top gate sidewall and bottom gate outer surface portion to electrically interconnect the top and bottom gate electrodes. The insulated channel region sidewall is insulated by an insulating sidewall spacer. The insulating sidewall spacer partially overlaps the top gate electrode electrically conductive sidewall. More generally beyond thin film transistor constructions, two conductive layers are provided which are separated by an insulating material on a semiconductor wafer. Each has an outer sidewall. An electrically conductive sidewall link is positioned over and electrically interconnects the respective outer sidewalls of the two conductive layers. Further, a mid conductive layer is provided which is electrically isolated from and positioned between the inner and outer conductive layers. This layer has a sidewall also covered by an insulating material. The insulating material partially overlaps the outer conductive layer sidewall. The electrically conductive sidewall link is positioned over the insulating material.
Inventors
- 👤 Charles H. Dennison
- 👤 Monte Manning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:13
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10B; H10B10/00; H10B10/12; H10B10/125; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
206 words
A bottom and top gated thin film transistor comprising: a conductive bottom thin film transistor gate electrode, the bottom gate electrode having a planarized outer surface, the outer surface having a surface area; a bottom gate dielectric layer atop the bottom gate electrode; a thin film transistor body layer over the bottom gate layer, the thin film transistor body layer having source, drain and channel regions, the channel region overlapping with the bottom gate electrode, the channel region having an insulated sidewall; a top gate dielectric layer over the thin film transistor body layer; an electrically conductive top thin film transistor gate electrode over the top gate dielectric layer, the top gate electrode overlapping with the channel region, the top gate electrode having an electrically conductive sidewall, the bottom gate electrode outer surface area including a portion extending outwardly beyond the top gate electrode sidewall; and an electrically conductive sidewall link overlying the electrically insulated channel region sidewall and extending between the top gate sidewall and bottom gate outer surface portion to electrically interconnect the top and bottom gate electrodes; wherein the insulated channel region sidewall is insulated by an insulating sidewall spacer, the insulating sidewall spacer partially overlapping the top gate electrode electrically conductive sidewall.
Claim 2
Dependent Claim
206 words
A bottom and top gated thin film transistor comprising: a conductive bottom thin film transistor gate electrode, the bottom gate electrode having a planarized outer surface, the outer surface having a surface area; a bottom gate dielectric layer atop the bottom gate electrode; a thin film transistor body layer over the bottom gate layer, the thin film transistor body layer having source, drain and channel regions, the channel region overlapping with the bottom gate electrode, the channel region having an insulated sidewall; a top gate dielectric layer over the thin film transistor body layer; an electrically conductive top thin film transistor gate electrode over the top gate dielectric layer, the top gate electrode overlapping with the channel region, the top gate electrode having an electrically conductive sidewall, the bottom gate electrode outer surface area including a portion extending outwardly beyond the top gate electrode sidewall; and an electrically conductive sidewall link overlying the electrically insulated channel region sidewall and extending between the top gate sidewall and bottom gate outer surface portion to electrically interconnect the top and bottom gate electrodes; wherein the insulated channel region sidewall is insulated by an insulating sidewall spacer, the insulating sidewall spacer partially overlapping the top gate electrode electrically conductive sidewall.
Claim 3
Dependent Claim
19 words
The bottom and top gated thin film transistor of claim 1 wherein the electrically conductive sidewall link comprises polysilicon.
Claim 4
Dependent Claim
106 words
An integrated circuit comprising: inner and outer conductive layers separated by an insulating material on a semiconductor wafer, the outer conductive layer having a sidewall, the inner conductive layer having an outer conductive surface; an electrically conductive sidewall link positioned over and electrically interconnecting the outer conductive layer sidewall and inner conductive layer outer conductive surface; and a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the insulating material partially overlapping the outer conductive layer sidewall, the electrically conductive sidewall link being positioned over the insulating material.
Claim 5
Dependent Claim
106 words
An integrated circuit comprising: inner and outer conductive layers separated by an insulating material on a semiconductor wafer, the outer conductive layer having a sidewall, the inner conductive layer having an outer conductive surface; an electrically conductive sidewall link positioned over and electrically interconnecting the outer conductive layer sidewall and inner conductive layer outer conductive surface; and a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the insulating material partially overlapping the outer conductive layer sidewall, the electrically conductive sidewall link being positioned over the insulating material.
Claim 6
Dependent Claim
109 words
An integrated circuit comprising: inner and outer conductive layers separated by an insulating material on a semiconductor wafer, the outer conductive layer having a sidewall, the inner conductive layer having an outer conductive surface; an electrically conductive sidewall link positioned over and electrically interconnecting the outer conductive layer sidewall and inner conductive layer outer conductive surface; and a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the insulating material partially overlapping the outer conductive layer sidewall, the electrically conductive sidewall link comprising polysilicon and being positioned over the insulating material.
Claim 7
Dependent Claim
109 words
An integrated circuit comprising: inner and outer conductive layers separated by an insulating material on a semiconductor wafer, the outer conductive layer having a sidewall, the inner conductive layer having an outer conductive surface; an electrically conductive sidewall link positioned over and electrically interconnecting the outer conductive layer sidewall and inner conductive layer outer conductive surface; and a mid conductive layer electrically isolated from and positioned between the inner and outer conductive layers, the mid conductive layer having a sidewall covered by an insulating material, the insulating material partially overlapping the outer conductive layer sidewall, the electrically conductive sidewall link comprising polysilicon and being positioned over the insulating material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |