Method of manufacturing a device comprising MIS transistors having a projecting gate on the weakly doped parts of source and drain regions

Claim 1

A method of manufacturing a semiconductor device comprising at least one transistor of the MIS type having a drain region and a source region each comprising a weakly doped part and a highly doped part slightly offset laterally with respect to the preceding part as well as a gate electrode covering the weakly doped part and extending laterally to the highly doped part, in which method there are successively effected on a semiconductor body covered by an insulating gate layer: a deposition of a first polycrystalline layer conducting by doping, the formation of a first insulating thin layer for later use as an etch stopper, a deposition of a second polycrystalline conducting layer which is thicker than the first polycrystalline layer, the formation of a second insulating layer which is thicker than the first insulating layer, the definition of gate islands by local etching of the second insulating layer and of the second polycrystalline layer outside the islands, the ion implantation of the weakly doped parts of the source and drain regions while using the gate islands as an implantation mask, the formation of insulating spacers on the edges of the gate islands by a deposition of a third insulating layer followed by an anisotropic etching of the major part of this layer, the insulating spacers limiting at their periphery widened gate islands, the removal by selective etching of the polycrystalline material exposed outside the widened gate islands, the ion implantation of the highly doped parts of the source and drain regions while using the widened gate islands as an implantation mask, and then the operations of finishing the deVice necessary for providing the contact connections and the interconnection with the active regions and with the gates of the transistors is characterized in that use is made of a first insulating layer having a thickness exceeding that which permits obtaining an electrical conduction between the first and second polycrystalline layers; in that, after having carried out the ion implantation of the weakly doped parts of the source and drain regions, the parts of the first insulating layer situated outside the gate islands are removed by etching; and in that then a third polycrystalline layer is deposited on the assembly, which is rendered conducting by doping before the insulating spacers are formed.

Claim 2

A method of manufacturing a semiconductor device comprising at least one transistor of the MIS type having a drain region and a source region each comprising a weakly doped part and a highly doped part slightly offset laterally with respect to the preceding part as well as a gate electrode covering the weakly doped part and extending laterally to the highly doped part, in which method there are successively effected on a semiconductor body covered by an insulating gate layer: a deposition of a first polycrystalline layer conducting by doping, the formation of a first insulating thin layer for later use as an etch stopper, a deposition of a second polycrystalline conducting layer which is thicker than the first polycrystalline layer, the formation of a second insulating layer which is thicker than the first insulating layer, the definition of gate islands by local etching of the second insulating layer and of the second polycrystalline layer outside the islands, the ion implantation of the weakly doped parts of the source and drain regions while using the gate islands as an implantation mask, the formation of insulating spacers on the edges of the gate islands by a deposition of a third insulating layer followed by an anisotropic etching of the major part of this layer, the insulating spacers limiting at their periphery widened gate islands, the removal by selective etching of the polycrystalline material exposed outside the widened gate islands, the ion implantation of the highly doped parts of the source and drain regions while using the widened gate islands as an implantation mask, and then the operations of finishing the deVice necessary for providing the contact connections and the interconnection with the active regions and with the gates of the transistors is characterized in that use is made of a first insulating layer having a thickness exceeding that which permits obtaining an electrical conduction between the first and second polycrystalline layers; in that, after having carried out the ion implantation of the weakly doped parts of the source and drain regions, the parts of the first insulating layer situated outside the gate islands are removed by etching; and in that then a third polycrystalline layer is deposited on the assembly, which is rendered conducting by doping before the insulating spacers are formed.