Patent US6845458B2 successfully refreshed from Google Patents.
US6845458B2
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System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines
Assignee: Round Rock Research LLC
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Filing: 2003-12-09
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Granted: 2005-01-18
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Expires: 2023-12-09
Abstract
Abstract An interleaved delay line for use in phase locked and delay locked loops is comprised of a first portion providing a variable amount of delay substantially independently of process, temperature and voltage (PVT) variations while a second portion, in series with the first portion, provides a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations. By combining, or interleaving, the two types of delay, single and dual locked loops constructed using the present invention achieve a desired jitter performance under PVT variations, dynamically track the delay variations of one coarse tap without a large number of delay taps, and provide for quick and tight locking. Methods of operating delay lines and locked loops are also disclosed.
Inventors
- 👤 Feng Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:50
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G11; G11C; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/0818; H03L7/085; H03L7/087; H03L7/099; H03L7/0995; H03L7/0998
Claims Analysis
Total Claims: 70
Claim 1
Independent Claim
99 words
A locked loop, comprising: a delay line having a first portion providing a variable amount of delay substantially independently of process, temperature and voltage variations and a second portion in series with said first portion and providing a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input o said delay line and to said phase detector.
Claim 2
Dependent Claim
99 words
A locked loop, comprising: a delay line having a first portion providing a variable amount of delay substantially independently of process, temperature and voltage variations and a second portion in series with said first portion and providing a variable amount of delay that substantially tracks changes in process, temperature, and voltage variations; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input o said delay line and to said phase detector.
Claim 3
Dependent Claim
36 words
The locked loop of claim 1 wherein said first portion of said delay line has a small intrinsic delay and said second portion of said delay line has a higher intrinic delay than said first portion.
Claim 4
Dependent Claim
42 words
The locked loop of claim 1 wherein in said first portion of said delay line the delay is varied by varying the load and in said second portion of said delay line the delay is varied by selecting a desired signal path.
Claim 5
Dependent Claim
21 words
The locked loop of claim 3 wherein the desired signal path is one of a slow path and a fast path.
Claim 6
Dependent Claim
26 words
The locked loop of claim 3 wherein the desired signal path is one of a series path through an inverter or a parallel path through inverters.
Claim 7
Dependent Claim
83 words
A locked loop, comprising: a delay line having a first portion providing a variable amount of delay with little intrinsic delay and a second portion providing a variable amount of delay with a larger intrinsic delay; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input of said delay line and to said phase detector.
Claim 8
Dependent Claim
83 words
A locked loop, comprising: a delay line having a first portion providing a variable amount of delay with little intrinsic delay and a second portion providing a variable amount of delay with a larger intrinsic delay; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input of said delay line and to said phase detector.
Claim 9
Dependent Claim
47 words
The locked loop of claim 6 wherein the delay of said first portion of said delay line is substantially independent of process, temperature and voltage variations and wherein the delay of the second portion of the delay line substantially tracks changes in process, temperature and voltage variations.
Claim 10
Dependent Claim
42 words
The locked loop of claim 6 wherein in said first portion of said delay line the delay is varied by varying the load and in said second portion of said delay line the delay is varied by selecting a desired signal path.
Claim 11
Dependent Claim
21 words
The locked loop of claim 8 wherein the desired signal path is one of a slow path and a fast path.
Claim 12
Dependent Claim
26 words
The locked loop of claim 8 wherein the desired signal path is one of a series path through an inverter or a parallel path through inverters.
Claim 13
Dependent Claim
97 words
A locked loop, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with the first circuit path and having a plurality of stages each having at least two paths; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path between an output of the second circuit path and an input of the first circuit path and said phase detector.
Claim 14
Dependent Claim
97 words
A locked loop, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with the first circuit path and having a plurality of stages each having at least two paths; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path between an output of the second circuit path and an input of the first circuit path and said phase detector.
Claim 15
Dependent Claim
25 words
The locked loop of claim 11 wherein said first circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 16
Dependent Claim
33 words
The locked loop of claim 11 wherein said first circuit path is substantially independent of process, temperature and voltage variations while said second circuit path substantially tracks changes in process, temperature and voltage.
Claim 17
Dependent Claim
17 words
The locked loop of claim 11 wherein the two paths include a fast and a slow path.
Claim 18
Dependent Claim
23 words
The locked loop of claim 11 wherein the two paths include a series path through an inverter and a parallel path through inverters.
Claim 19
Dependent Claim
88 words
A locked loop, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associated therewith; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; and a feedback path between an output of the second circuit path and an input of the first circuit path and said phase detector.
Claim 20
Dependent Claim
88 words
A locked loop, comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associated therewith; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; and a feedback path between an output of the second circuit path and an input of the first circuit path and said phase detector.
Claim 21
Dependent Claim
25 words
The locked loop of claim 16 wherein said first circuit path as an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 22
Dependent Claim
33 words
The locked loop of claim 16 wherein said first circuit path is substantially independent of process, temperature and voltage variations while said second circuit path substantially tracks changes in process, temperature and voltage.
Claim 23
Dependent Claim
115 words
A locked loop, comprising: a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; a second circuit path in series with said first circuit path and having a plurality of stages each having at least a fast and a slow path; a control circuit for controlling the number of stages in said first circuit the and the number of fast paths and slow paths in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said first circuit path to an in input of said second circuit path and said phase detector.
Claim 24
Dependent Claim
115 words
A locked loop, comprising: a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; a second circuit path in series with said first circuit path and having a plurality of stages each having at least a fast and a slow path; a control circuit for controlling the number of stages in said first circuit the and the number of fast paths and slow paths in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said first circuit path to an in input of said second circuit path and said phase detector.
Claim 25
Dependent Claim
25 words
The locked loop of claim 19 wherein said first circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 26
Dependent Claim
142 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a delay line having a first portion providing a variable amount of delay substantially independently of process, temperature and voltage variations and a second portion in series with said first portion and providing a variable amount of delay that substantially track changes in process, temperature, and voltage variations; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input o said first locked loop and to said phase detector, said output signal being available at said output of said delay line.
Claim 27
Dependent Claim
142 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a delay line having a first portion providing a variable amount of delay substantially independently of process, temperature and voltage variations and a second portion in series with said first portion and providing a variable amount of delay that substantially track changes in process, temperature, and voltage variations; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input o said first locked loop and to said phase detector, said output signal being available at said output of said delay line.
Claim 28
Dependent Claim
37 words
The dual locked loop of claim 21 wherein said first portion of said delay line has a small intrinsic delay and said second portion of said delay line has a higher intrinsic delay than said first portion.
Claim 29
Dependent Claim
43 words
The dual locked loop of claim 21 wherein in said first portion of said delay line the delay is varied by varying the load and in said second portion of said delay line the delay is varied by selecting a desired signal path.
Claim 30
Dependent Claim
22 words
The dual locked loop of claim 23 wherein the desired signal path is one of a slow path and a fast path.
Claim 31
Dependent Claim
27 words
The dual locked loop of claim 23 wherein the desired signal path is one of a series path through an inverter and a parallel path through inverters.
Claim 32
Dependent Claim
126 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a delay line having a first portion providing a variable amount of delay with little intrinsic delay and a second portion providing a variable amount of delay with a larger intrinsic delay; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input of said first locked loop and to said phase detector, said output signal being available at said output of said delay line.
Claim 33
Dependent Claim
126 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a delay line having a first portion providing a variable amount of delay with little intrinsic delay and a second portion providing a variable amount of delay with a larger intrinsic delay; a control circuit for controlling the delay of said delay line; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said delay line to an input of said first locked loop and to said phase detector, said output signal being available at said output of said delay line.
Claim 34
Dependent Claim
48 words
The dual locked loop of claim 26 wherein the delay of said first portion of said delay line is substantially independent of process, temperature and voltage variations and wherein the delay of the second portion of the delay line substantially tracks changes in process, temperature and voltage variations.
Claim 35
Dependent Claim
44 words
The dual locked loop of claim 26 wherein in said first portion of said delay line the delay is varied by varying the load and in said second portion of said de ay line the delay is varied by selecting a desired signal path.
Claim 36
Dependent Claim
22 words
The dual locked loop of claim 28 wherein the desired signal path is one of a slow path and a fast path.
Claim 37
Dependent Claim
27 words
The dual locked loop of claim 28 wherein the desired signal path is one of a series path through an inverter and a parallel path through inverters.
Claim 38
Dependent Claim
142 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with the first circuit path and having a plurality of stages each having at least two paths; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said second locked loop to an input of said first locked loop and to said phase detector, said output signal being available at said output of said second locked loop.
Claim 39
Dependent Claim
142 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a first circuit path having a stepwise variable capacitive load; a second circuit path in series with the first circuit path and having a plurality of stages each having at least two paths; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said second locked loop to an input of said first locked loop and to said phase detector, said output signal being available at said output of said second locked loop.
Claim 40
Dependent Claim
26 words
The dual locked loop of claim 31 wherein said first circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 41
Dependent Claim
34 words
The dual locked loop of claim 31 wherein said first circuit path is substantially independent of process, temperature and voltage variations while said second circuit path substantially tracks changes in process, temperature and voltage.
Claim 42
Dependent Claim
17 words
The locked loop of claim 31 wherein the two paths include a fast and a slow path.
Claim 43
Dependent Claim
23 words
The locked loop of claim 31 wherein the two paths include a series path through an inverter and a parallel path through inverters.
Claim 44
Dependent Claim
138 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a first circuit path having a stepwise variable capacitive load and a second circuit path having a plurality of stages each having a variable amount of drive associated therewith; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said second locked loop to an input of said first locked loop and to said phase detector, said output signal being available at said output of said second locked loop.
Claim 45
Dependent Claim
138 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a first circuit path having a stepwise variable capacitive load and a second circuit path having a plurality of stages each having a variable amount of drive associated therewith; a control circuit for controlling the amount of capacitance in said first circuit path and the number of stages in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said second locked loop to an input of said first locked loop and to said phase detector, said output signal being available at said output of said second locked loop.
Claim 46
Dependent Claim
26 words
The dual locked loop of claim 36 wherein said first circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 47
Dependent Claim
34 words
The dual locked loop of claim 36 wherein said first circuit path is substantially independent of process, temperature and voltage variations while said second circuit path substantially tracks changes in process, temperature and voltage.
Claim 48
Dependent Claim
143 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a first circuit path having a plurality of stages each having a variable amount of drive associated therewith and a second circuit path in series with said first circuit path and having a plurality of stages each having at least a fast and a slow path; a control circuit for controlling the number of stages in said first circuit and the number of fast paths and slow paths in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said second circuit to an input of said first circuit and to said phase detector.
Claim 49
Dependent Claim
143 words
A dual locked loop, comprising: a first locked loop for establishing a phase relationship between an output signal and a reference signal; a second locked loop responsive to said first locked loop and comprising: a first circuit path having a plurality of stages each having a variable amount of drive associated therewith and a second circuit path in series with said first circuit path and having a plurality of stages each having at least a fast and a slow path; a control circuit for controlling the number of stages in said first circuit and the number of fast paths and slow paths in said second circuit path; a phase detector for producing signals for input to said control circuit; and a feedback path for connecting an output of said second circuit to an input of said first circuit and to said phase detector.
Claim 50
Dependent Claim
26 words
The dual locked loop of claim 39 wherein said first circuit path has an intrinsic delay smaller than the intrinsic delay of said second circuit path.
Claim 51
Independent Claim
85 words
A method of operating a locked loop, comprising: propagating a signal through two different types of variable delay circuits, a first circuit being substantially independent of process, temperature and voltage variations and a second circuit tracking changes in process, temperature and voltage variation; feeding back the propagated signal to the input of one of the delay circuits and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second delay circuits.
Claim 52
Independent Claim
85 words
A method of operating a locked loop, comprising: propagating a signal through two different types of variable delay circuits, a first circuit being substantially independent of process, temperature and voltage variations and a second circuit tracking changes in process, temperature and voltage variation; feeding back the propagated signal to the input of one of the delay circuits and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second delay circuits.
Claim 53
Independent Claim
74 words
A method of operating a locked loop, comprising: propagating a signal through two different types of series-connected delay circuits, one circuit having a small intrinsic delay and the other circuit having a larger trinsic delay; feeding back the propagated signal to the input of one of the delay circuits and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said delay circuits.
Claim 54
Independent Claim
74 words
A method of operating a locked loop, comprising: propagating a signal through two different types of series-connected delay circuits, one circuit having a small intrinsic delay and the other circuit having a larger trinsic delay; feeding back the propagated signal to the input of one of the delay circuits and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said delay circuits.
Claim 55
Independent Claim
90 words
A method of operating a locked loop, comprising: propagating a signal through a first circuit path having a stepwise variable capacitive load; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having at least two paths; feeding back the propagated signal to the input of the first circuit path an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 56
Independent Claim
90 words
A method of operating a locked loop, comprising: propagating a signal through a first circuit path having a stepwise variable capacitive load; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having at least two paths; feeding back the propagated signal to the input of the first circuit path an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 57
Independent Claim
93 words
A method of operating a locked loop, comprising: propagating a signal through a first circuit path having a stepwise variable capacitive load; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associate therewith; feeding back the propagated signal to the input of the first circuit path and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 58
Independent Claim
93 words
A method of operating a locked loop, comprising: propagating a signal through a first circuit path having a stepwise variable capacitive load; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associate therewith; feeding back the propagated signal to the input of the first circuit path and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 59
Independent Claim
101 words
A method of operating a locked loop, comprising: propagating a signal through a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; propagating said signal through a second circuit path in series with said first circuit and having a plurality of stages each having at least a fast and a slow path; feeding back the propagated signal to the input of the first circuit path and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 60
Independent Claim
101 words
A method of operating a locked loop, comprising: propagating a signal through a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; propagating said signal through a second circuit path in series with said first circuit and having a plurality of stages each having at least a fast and a slow path; feeding back the propagated signal to the input of the first circuit path and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 61
Independent Claim
106 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through two different types of variable delay circuits, a first circuit being substantially independent of process, temperature and voltage variations and a second circuit tracking changes in process, temperature and voltage variations; feeding back the propagated signal to the input of the first locked loop an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second delay circuits.
Claim 62
Independent Claim
106 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through two different types of variable delay circuits, a first circuit being substantially independent of process, temperature and voltage variations and a second circuit tracking changes in process, temperature and voltage variations; feeding back the propagated signal to the input of the first locked loop an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second delay circuits.
Claim 63
Independent Claim
94 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through two different types of delay circuits, one circuit having a small intrinsic delay and the other circuit having a larger intrinsic delay; feeding back the propagated signal to the input of the first locked loop an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said delay circuits.
Claim 64
Independent Claim
94 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through two different types of delay circuits, one circuit having a small intrinsic delay and the other circuit having a larger intrinsic delay; feeding back the propagated signal to the input of the first locked loop an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said delay circuits.
Claim 65
Independent Claim
120 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through a first circuit path in series with said first locked loop and having a stepwise variable capacitive load; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having at least two paths; feeding back the propagated signal to the input of the first locked loop and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 66
Independent Claim
120 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through a first circuit path in series with said first locked loop and having a stepwise variable capacitive load; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having at least two paths; feeding back the propagated signal to the input of the first locked loop and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 67
Independent Claim
116 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through a first circuit path having a stepwise variable capacitive load; propagating said second signal through a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associated therewith; feeding back the propagated signal to the input of the first locked loop an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 68
Independent Claim
116 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through a first circuit path having a stepwise variable capacitive load; propagating said second signal through a second circuit path in series with said first circuit path and having a plurality of stages each having a variable amount of drive associated therewith; feeding back the propagated signal to the input of the first locked loop an a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 69
Independent Claim
122 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having at least fast and slow paths; feeding back the propagated signal to the input of the first locked loop and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
Claim 70
Independent Claim
122 words
A method of operating a dual locked loop, comprising: propagating a signal through a first locked loop to establish a phase relationship between an output signal and a reference signal; propagating said signal through a first circuit path having a plurality of stages each having a variable amount of drive associated therewith; propagating said signal through a second circuit path in series with said first circuit path and having a plurality of stages each having at least fast and slow paths; feeding back the propagated signal to the input of the first locked loop and a phase detector; and detecting a phase difference between said feedback signal and a reference signal to produce control signals for said first and second circuit paths.
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