Method and apparatus for complete functional testing of a complex signal path of a semiconductor chip

Claim 2

Method for testing logic devices of a complex signal path of a semiconductor chip, said logic devices including at least a measurement latch circuit, said method comprising the steps of: placing said chip in a test mode in response to first control signals and forcing a sequence of unasserted bits into a measurement delay line circuit having signal outputs connected to said measurement latch circuit, and further placing said chip in a plurality of sub-test modes in response to second control signals to enable complete functional testing of said logic devices of said complex signal path; shifting a selected pattern of asserted bits into a test register, located on said chip, in response to a clocking signal, said test register being connected to said measurement latch circuit, said selected pattern of asserted bits comprising a test pattern; loading said test pattern from said test register into said measurement latch circuit and thereafter into said logic devices of said complex signal path when said chip is placed in a measurement test sub-mode of said test mode, said test pattern overriding the signal outputs of said measurement delay line; generating timing signals with a control logic unit to activate said logic devices of said signal path during said measurement sub-mode; and sampling an output clock signal of said chip to determine whether said clock signal is present at the output line of said chip, whereby the presence of said output clock signal indicates that said logic devices of said complex signal path exercised by said test pattern are functional.

Claim 3

Apparatus for testing logic circuits in a complex signal path in a semiconductor chip, said logic circuits including a measurement latch and decoder circuit connected to a plurality of delay adjusting units configured to produce a delay-regulated clock signal at the output of said chip, the sequencing of operations of said logic circuits being initiated by a signal path control logic unit in accordance with a measurement regulation cycle, said apparatus comprising: a test register located on said chip, said test register having a serial input connected to a source of a signal in a predetermined logical state and having a plurality of outputs connected to corresponding ones of a plurality of inputs of latch devices of said measurement latch and decoder circuit, said latch devices further having a plurality of outputs connected to corresponding inputs of a decoder circuit of said measurement latch and decoder circuit; and a mode control logic unit for placing said semiconductor chip in a test mode of operation in response to first control signals, said mode control logic unit further generating first and second timing signals in response to a plurality of second control signals that place said semiconductor chip in a plurality of sub-test modes of operation, said sub-test modes of operation including: a reset mode for placing said signal path control logic unit in a known state of said measurement regulation cycle in response to said first timing signal; a shift mode for loading a pattern of said predetermined logical signal states into said test register in response to said second timing signal; and a measurement test mode for loading said pattern of predetermined logical signal states from said test register into said logic circuits of said signal path in accordance with said measurement regulation cycle, wherein said pattern of predetermined logical signal states propagates through said logic circuits and said delay-regulated clock signal at the output of said chip is sampled to determine successful testing of said logic circuits.

Claim 4

Apparatus for testing logic circuits in a complex signal path in a semiconductor chip, said logic circuits including a measurement latch and decoder circuit connected to a plurality of delay adjusting units configured to produce a delay-regulated clock signal at the output of said chip, the sequencing of operations of said logic circuits being initiated by a signal path control logic unit in accordance with a measurement regulation cycle, said apparatus comprising: a test register located on said chip, said test register having a serial input connected to a source of a signal in a predetermined logical state and having a plurality of outputs connected to corresponding ones of a plurality of inputs of latch devices of said measurement latch and decoder circuit, said latch devices further having a plurality of outputs connected to corresponding inputs of a decoder circuit of said measurement latch and decoder circuit; and a mode control logic unit for placing said semiconductor chip in a test mode of operation in response to first control signals, said mode control logic unit further generating first and second timing signals in response to a plurality of second control signals that place said semiconductor chip in a plurality of sub-test modes of operation, said sub-test modes of operation including: a reset mode for placing said signal path control logic unit in a known state of said measurement regulation cycle in response to said first timing signal; a shift mode for loading a pattern of said predetermined logical signal states into said test register in response to said second timing signal; and a measurement test mode for loading said pattern of predetermined logical signal states from said test register into said logic circuits of said signal path in accordance with said measurement regulation cycle, wherein said pattern of predetermined logical signal states propagates through said logic circuits and said delay-regulated clock signal at the output of said chip is sampled to determine successful testing of said logic circuits.

Claim 5

The apparatus of claim 2 wherein said test register comprises a plurality of cascaded flip-flop devices configured as a shift register.

Claim 6

The apparatus of claim 3 wherein said plurality of cascaded flip-flop devices are arranged such that the D-input of a first of said cascaded devices is connected to said source and the Q-outputs of each of said cascaded devices are connected to the D-inputs of each adjacent of said cascaded devices.

Claim 7

The apparatus of claim 4 wherein each of said Q-outputs of said cascaded flip-flop devices is connected to a set input of a corresponding one of said latch devices.

Claim 8

The apparatus of claim 5 wherein said first control signals include a MODE signal and a LOOPIN signal.

Claim 9

The apparatus of claim 6 wherein said second control signals include a PH90 -- H signal and a PH90 -- L signal.

Claim 10

The apparatus of claim 7 wherein said first timing signal generated by said mode control logic unit is a SMCLR signal used to clear a sequential logic circuit of said signal path control logic unit.

Claim 11

The apparatus of claim 8 wherein said second timing signal generated by said mode control logic unit is a TC signal used to clock said plurality of cascaded flip-flop devices of said test register.

Claim 12

The apparatus of claim 2 wherein said signal path control logic unit comprises two cascaded Johnson counters coupled to a decoder and synchronizer unit.

Claim 13

The apparats of claim 10 wherein said predetermined logical signal sate is a hardwired logical "1" signal.