US5808478A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading
Assignee: Texas Instruments Inc
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Filing: 1997-02-21
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Granted: 1998-09-15
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Expires: 2017-02-21
Abstract
Abstract An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18). If the transition on the output terminal (12) occurs after the delayed transition, then the counter (74) increments the count value in the opposite direction, increasing the drive to the load (18) to increase the speed of the output driver (14).
Inventors
- 👤 Bernhard Hans Andresen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:33
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585; H03K19/0005; H03K19/003; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
132 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal; a second latch for receiving the delayed signal and also for receiving the second input signal; logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the logic circuitry comprises an XOR gate and a NOR gate wherein the XOR gate receives the output of the first latch and the output of the second latch and the NOR gate receives an output of the XOR gate and the first input signal.
Claim 2
Dependent Claim
132 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal; a second latch for receiving the delayed signal and also for receiving the second input signal; logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the logic circuitry comprises an XOR gate and a NOR gate wherein the XOR gate receives the output of the first latch and the output of the second latch and the NOR gate receives an output of the XOR gate and the first input signal.
Claim 3
Dependent Claim
117 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal, a second latch for receiving the delayed signal and also for receiving the second input signal, logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the counter comprises an up/down counter with a clock input for receiving the output of the logic circuitry and a count input for receiving the output of the first latch.
Claim 4
Dependent Claim
117 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal, a second latch for receiving the delayed signal and also for receiving the second input signal, logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the counter comprises an up/down counter with a clock input for receiving the output of the logic circuitry and a count input for receiving the output of the first latch.
Claim 5
Dependent Claim
100 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal, a second latch for receiving the delayed signal and also for receiving the second input signal; logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the delay element comprises a variable delay which is controlled by compensation circuitry.
Claim 6
Dependent Claim
100 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal, a second latch for receiving the delayed signal and also for receiving the second input signal; logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the delay element comprises a variable delay which is controlled by compensation circuitry.
Claim 7
Dependent Claim
111 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal, a second latch for receiving the delayed signal and also for receiving the second input signal: logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the first input signal comprises the input of a buffer being driven and the second input signal the output of said buffer being driven.
Claim 8
Dependent Claim
111 words
A control circuit for driving a buffer, the control circuit comprising: a delay element for receiving a first input signal and generating a delayed signal; a first latch for receiving the delayed signal and also for receiving a second input signal, a second latch for receiving the delayed signal and also for receiving the second input signal: logic circuitry coupled to an output of the first latch and to an output of the second latch; a counter coupled to the output of the logic circuitry; and wherein the first input signal comprises the input of a buffer being driven and the second input signal the output of said buffer being driven.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |