Digital phase-locked loop circuit with reduced phase jitter frequency

Claim 2

A digital phase-locked loop circuit, comprising: a phase detector, having a first input for receiving a system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other; a latch, for storing the state of the direction signal; an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal; a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal; a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; and clock distribution circuitry, for receiving the first delayed clock and for distributing one or more chip clocks based thereupon.

Claim 3

The digital phase-locked loop of claim 1 , wherein the first gate is for passing shift signals to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch do not differ from the current state of the direction signal.

Claim 4

The digital phase-locked loop of claim 1 , further comprising: a second gate, having a first input coupled to the output of the exclusive-OR function, and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch do not differ from the current state of the direction signal.

Claim 5

The digital phase-locked loop of claim 3 , wherein the second gate is for passing shift signals to the shift clock input of the second digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal.

Claim 6

The digital phase-locked loop of claim 1 , wherein the latch has a clock input for receiving a clock signal, responsive to which the state of the direction signal is stored; and wherein the shift clock output of the phase detector is coupled to the clock input of the latch.

Claim 7

The digital phase-locked loop of claim 5 , wherein the shift clock output of the phase detector is coupled to the clock input of the latch in such a manner that the latch stores the state of the direction signal responsive to a trailing edge of the shift signal.

Claim 8

The digital phase-locked loop of claim 1 , further comprising: a clock buffer having an input coupled to receive the first delayed signal from the first digital delay line, and having an output coupled to the clock distribution circuitry.

Claim 11

The method of claim 8 , wherein the step of incrementally varying the delay length of the first digital delay line comprises: responsive to the direction signal indicating that the feedback clock leads the system clock, lengthening the delay length of the first digital delay line; and responsive to the direction signal indicating that the feedback clock lags the system clock, reducing the delay length of the first digital delay line.

Claim 12

The method of claim 9 , further comprising: responsive to the monitoring step detecting that corresponding edges of the system clock and the feedback clock differ in time by more than a selected threshold, generating a shift clock pulse; wherein the lengthening and reducing steps are performed responsive to the first digital delay line receiving the shift clock pulse at a shift clock input.

Claim 13

The method of claim 10 , further comprising: responsive to the comparing step indicating that the stored direction signal matches the current state of the direction signal, applying the shift clock pulse to a shift clock input of the first digital delay line; and responsive to the comparing step indicating that the stored direction signal does not match the current state of the direction signal, blocking the shift clock pulse from the shift clock input of the first digital delay line.

Claim 14

The method of claim 9 , wherein the step of incrementally varying the delay length of the second digital delay line comprises: responsive to the direction signal indicating that the feedback clock leads the system clock, lengthening the delay length of the second digital delay line; and responsive to the direction signal indicating that the feedback clock lags the system clock, reducing the delay length of the second digital delay line.

Claim 15

The method of claim 10 , further comprising: responsive to the monitoring step detecting that corresponding edges of the system clock and the feedback clock differ in time by more than a selected threshold, generating a shift clock pulse; wherein the step of incrementally varying the delay length of the second digital delay line comprises: responsive to the direction signal indicating that the feedback clock leads the system clock, lengthening the delay length of the second digital delay line; and responsive to the direction signal indicating that the feedback clock lags the system clock, reducing the delay length of the second digital delay line; and wherein the lengthening and reducing steps are performed responsive to the first digital delay line receiving the shift clock pulse at a shift clock input.

Claim 16

The method of claim 13 , further comprising: responsive to the comparing step indicating that the stored direction signal does not match the current state of the direction signal, applying the shift clock pulse to a shift clock input of the second digital delay line; and responsive to the comparing step indicating that the stored direction signal matches the current state of the direction signal, blocking the shift clock pulse from the shift clock input of the second digital delay line.

Claim 17

An integrated circuit, comprising: a logic function, having a clock input; and a digital phase-locked loop, comprising: a phase detector, having a first input for receiving a system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to a detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other; a latch, for storing the state of the direction signal; an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal; a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal; a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; and clock distribution circuitry, for receiving the first delayed clock and for applying, to the clock input of the logic function, a chip clock based upon the first delayed clock.

Claim 18

An integrated circuit, comprising: a logic function, having a clock input; and a digital phase-locked loop, comprising: a phase detector, having a first input for receiving a system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to a detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other; a latch, for storing the state of the direction signal; an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal; a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal; a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; and clock distribution circuitry, for receiving the first delayed clock and for applying, to the clock input of the logic function, a chip clock based upon the first delayed clock.

Claim 19

The integrated circuit of claim 15 , wherein the digital phase locked loop further comprises: a second gate, having a first input coupled to the output of the exclusive-OR function, and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch do not differ from the current state of the direction signal.

Claim 20

An electronic system, comprising: a clock generator circuit for generating a system clock; a plurality of integrated circuits, at least one of the plurality of integrated circuits comprising: a logic function, having a clock input; and a digital phase-locked loop, comprising: a phase detector, having a first input for receiving the system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other; a latch, for storing the state of the direction signal; an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal; a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal; a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; and clock distribution circuitry, for receiving the first delayed clock and for applying, to the clock input of the logic function, a chip clock based upon the first delayed clock.

Claim 21

An electronic system, comprising: a clock generator circuit for generating a system clock; a plurality of integrated circuits, at least one of the plurality of integrated circuits comprising: a logic function, having a clock input; and a digital phase-locked loop, comprising: a phase detector, having a first input for receiving the system clock and a second input for receiving a feedback clock, for generating a shift signal at a shift clock output responsive to detecting a phase difference between the system and feedback clocks, and for generating a direction signal at a direction output indicating which of the system and feedback clocks leads the other; a latch, for storing the state of the direction signal; an exclusive-OR function, having a first input coupled to the output of the latch and a second input coupled to receive the direction signal from the phase detector, for comparing the contents of the latch corresponding to a stored state of the direction signal with the current state of the direction signal; a first digital delay line, having an input coupled to receive the system clock, for generating a first delayed clock from the system clock, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the first digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; a first gate, having a first input coupled to the output of the exclusive-OR function and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch differ from the current state of the direction signal; a second digital delay line, having an input coupled to receive the first delayed clock, for generating the feedback clock therefrom, the first digital delay line having a direction input coupled to the direction output of the phase detector, and having a shift clock input, the second digital delay line having a delay length that is selectively incremented or decremented according to a signal at its direction input, responsive to receiving a shift signal at the shift clock input; and clock distribution circuitry, for receiving the first delayed clock and for applying, to the clock input of the logic function, a chip clock based upon the first delayed clock.

Claim 22

The system of claim 17 , wherein the digital phase locked loop in the one of the plurality of integrated circuits further comprises: a second gate, having a first input coupled to the output of the exclusive-OR function, and having a second input coupled to the shift clock output of the phase detector, for blocking shift signals from being applied to the shift clock input of the first digital delay line responsive to the exclusive-OR function determining that the contents of the latch do not differ from the current state of the direction signal.