Precision digital phase lock loop circuit

Claim 2

A precision digital phase lock loop circuit, comprising: a serial shift register for receiving digital input pulses and producing time-delayed digital output pulses from the input pulses; a clock generator for applying clock pulses to said shift register to drive it and set the time delay and thereby the phase shift of the output pulses, said generator having a resistance; a digitally-controlled potentiometer unit connected in series with said clock generator and being adjustable to change the resistance of said potentiometer unit in increments in order to adjust the resistance of said clock generator and thereby set the frequency of the clock pulses applied to said shift register and the time delay produced by said shift register; and a feedback control arrangement for receiving the same input pulses as received by said shift register and detecting the periods of these input pulses, said feedback control arrangement also for receiving other pulses from an external source representing desired phase shifts of the output signals of said shift register and, in response to receiving the input pulses and the other pulses, adjusting in increments the resistance of said potentiometer unit and thereby setting the desired frequency of the clock pulses generated by said clock generator and the phase shifts of the output pulses produced by said shift register.

Claim 3

The circuit of claim 1 wherein said feedback control arrangement includes a control unit, a memory unit, and a potentiometer adjustment unit, said memory unit being interposed in series between said control and potentiometer adjustment units.

Claim 4

The circuit of claim 2 wherein said potentiometer unit includes a plurality of potentiometer modules connected in series with one another and with said clock generator, said potentiometer modules also being connected in parallel with said potentiometer adjustment

Claim 5

The circuit of claim 2 wherein said memory unit is a programmable read-only memory.

Claim 6

The circuit of claim 2 wherein said control unit receives the same digital input pulses as received by said shift register and detects the periods of these input pulses by counting and produces control pulses proportional to the detected periods.

Claim 7

The circuit of claim 5 wherein said control unit includes: a flip-flop, a clock, and a first counter, said clock being connected between said flip-flop and said first counter; said flip-flop being operable for sensing the beginning and end of one period between consecutive input pulses and causing said clock to start and stop application of clock pulses to said first counter in correspondence to the beginning and end of the one period; said first counter, in response to application of the clock pulses, being operable to start counting and outputting clock pulses in correspondence to the beginning and end of the one period, the number of clock pulses outputted by said first counter being a multiple of the number of clock pulses received by said first counter from said clock.

Claim 8

The circuit of claim 6 wherein said control unit also includes: a multiplexer having select inputs, a second counter, and a third counter, said multiplexer being connected between said first and second counters, said third counter being connected between said second counter and said select inputs of said multiplexer; said second counter receiving the multiplied clock pulses from said first counter via said multiplexer and outputting said control pulses; said third counter receiving at least one of the control pulses from said second counter and being operable to control said select inputs of said multiplexer for ensuring that the multiplied clock pulses sent each period from said first counter to said second counter via said are multiplexer are adjusted in number to compensate for any variation in frequency of input pulses received by said flip-flop such that accurate operation of said circuit can be maintained independent of input pulse frequency.

Claim 9

The circuit of claim 5 wherein said memory unit stores a look-up table of values representing an array of different counts of increments by which the resistance of said potentiometer unit can be adjusted.

Claim 10

The circuit of claim 8 wherein said memory unit is accessed by input signals which identify different addresses of said memory unit.

Claim 11

The circuit of claim 9 wherein said input signals are composed of the control pulses from said control unit and the other pulses from said external source defining different desired phase shifts of the output pulses.

Claim 12

The circuit of claim 10 wherein said potentiometer adjustment unit receives output signals produced by said memory unit and adjusts the resistance of said potentiometer unit by the counts of increments stored at the accessed addresses of said memory unit and thereby sets the desired frequency of the clock pulses generated by said clock generator and the phase shifts of the output pulses produced by said shift register.

Claim 13

The circuit of claim 11 wherein said potentiometer unit is a plurality of potentiometer modules connected in series with one another and with said clock generator, said potentiometer modules also being connected in parallel with said potentiometer adjustment unit.

Claim 14

The circuit of claim 11 wherein said potentiometer adjustment unit includes: a counter connected to the memory unit for receiving the output signals from the memory unit and providing the correct count stored at the accessed address of said memory unit to use in adjusting the resistance of said potentiometer unit; and an array of programmable logic connected to said counter and said potentiometer unit for adjusting the resistance of said potentiometer unit by applying the correct count of increments provided by said counter to said potentiometer unit.

Claim 15

A precision digital phase lock loop circuit, comprising: a serial shift register for receiving digital input pulses and producing time-delayed digital output pulses from the input pulses; a clock generator for applying clock pulses to said shift register to drive it and set the time delay and thereby the phase shift of the output pulses, said generator having a resistance; a potentiometer unit composed of a plurality of digitally-controlled potentiometer modules connected in series with one another and with said clock generator and being adjustable to change the resistance of said potentiometer unit in increments in order to adjust the resistance of said clock generator and thereby set the frequency of the clock pulses applied to said shift register and the time delay produced by said shift register; and a feedback control arrangement including a control unit, a potentiometer adjustment unit, and a programmable read-only memory unit connected in series between said control unit and said adjustment unit, said read-only memory unit storing a look-up table of values representing an array of different counts of increments by which the resistance of said potentiometer unit can be adjusted; said control unit for receiving the same digital input pulses as received by said shift register and detecting the periods of these input pulses by counting and, in response thereto, producing control pulses proportional to the detected periods; said read-only memory unit having accessible addresses for storing count values, said unit for receiving said control pulses from said control unit and receiving other pulses from an external source representing desired phase shifts of the output signals of said shift register and, in response thereto, producing output signals; said potentiometer adjustment unit receiving the output signals produced by said memory unit and adjusting the resistance of said potentiometer unit by applying the count of increments stored at the accessed address of said memory unit to said potentiometer unit and thereby setting the desired frequency of the clock pulses generated by said clock generator and the phase shifts of the output pulses produced by said shift register.

Claim 16

A precision digital phase lock loop circuit, comprising: a serial shift register for receiving digital input pulses and producing time-delayed digital output pulses from the input pulses; a clock generator for applying clock pulses to said shift register to drive it and set the time delay and thereby the phase shift of the output pulses, said generator having a resistance; a potentiometer unit composed of a plurality of digitally-controlled potentiometer modules connected in series with one another and with said clock generator and being adjustable to change the resistance of said potentiometer unit in increments in order to adjust the resistance of said clock generator and thereby set the frequency of the clock pulses applied to said shift register and the time delay produced by said shift register; and a feedback control arrangement including a control unit, a potentiometer adjustment unit, and a programmable read-only memory unit connected in series between said control unit and said adjustment unit, said read-only memory unit storing a look-up table of values representing an array of different counts of increments by which the resistance of said potentiometer unit can be adjusted; said control unit for receiving the same digital input pulses as received by said shift register and detecting the periods of these input pulses by counting and, in response thereto, producing control pulses proportional to the detected periods; said read-only memory unit having accessible addresses for storing count values, said unit for receiving said control pulses from said control unit and receiving other pulses from an external source representing desired phase shifts of the output signals of said shift register and, in response thereto, producing output signals; said potentiometer adjustment unit receiving the output signals produced by said memory unit and adjusting the resistance of said potentiometer unit by applying the count of increments stored at the accessed address of said memory unit to said potentiometer unit and thereby setting the desired frequency of the clock pulses generated by said clock generator and the phase shifts of the output pulses produced by said shift register.

Claim 17

The circuit of claim 14 wherein said plurality of potentiometer modules are connected in parallel with said potentiometer adjustment unit.

Claim 18

The circuit of claim 14 wherein said control unit includes: a flip-flop, a clock, and a first counter, said clock being connected between said flip-flop and said first counter; said flip-flop being operable for sensing the beginning and end of one period between consecutive input pulses and causing said clock to start and stop application of clock pulses to said first counter in correspondence to the beginning and end of the one period; said first counter, in response to application of the clock pulses, being operable to start counting and outputting clock pulses in correspondence to the beginning and end of the one period, the number of clock pulses outputted by said first counter being a multiple of the number of clock pulses received by said first counter from said clock.

Claim 19

The circuit of claim 16 wherein said control unit also include: a multiplexer, a second counter, and a third counter, said multiplexer being connected between said first and second counters, said third counter being connected between said second counter and select inputs of said multiplexer; said second counter receiving the multiplied clock pulses from said first counter via said multiplexer and outputting said control pulses; said third counter receiving at least one of the control pulses from said second counter and being operable to control said select inputs of said multiplexer for ensuring that the multiplied clock pulses sent each period from said first counter to said second counter via are multiplexer are adjusted in number to compensate for any variation in frequency of input pulses received by said flip-flop such that accurate operation of said circuit can be maintained independent of input pulse frequency.

Claim 20

The circuit of claim 14 wherein said read-only memory unit connected to said control unit is accessed by input signals which identify different addresses of said memory unit.

Claim 21

The circuit of claim 18 wherein said input signals are composed of the control pulses from said control unit and the other pulses from said external source defining different desired phase shifts of the output pulses.

Claim 22

The circuit of claim 14 wherein said potentiometer adjustment unit includes: a counter connected to the memory unit for receiving the output signals from the memory unit and providing the correct count stored at the accessed address of said memory unit to use in adjusting the resistance of said potentiometer unit; and an array of programmable logic connected to said counter and said potentiometer unit for adjusting the resistance of said potentiometer unit by applying the correct count of increments provided by said counter to said potentiometer unit.