US6131168A
Expired / Lapsed
US
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System and method for reducing phase error in clocks produced by a delay locked loop
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1999-03-18
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Granted: 2000-10-10
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Expires: 2019-03-18
Abstract
Abstract A circuit and method for reducing error in a delay locked loop (DLL) in which a plurality of outputs, each establishing a boundary between two consecutive phases, is accomplished by averaging an error present in one of the outputs over at least two phases established by the outputs. A pair of inverters are used to drive fight during a definable time period, which enables the circuitry to average the error over at least two phases, thus distributing the error that was present in one phase over at least two phases.
Inventors
- 👤 Richard A. Krzyzkowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:14
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
135 words
A system for clocking in an integrated circuit, comprising: a delay locked loop (DLL) having a plurality of delay lines, each delay line having an output, each output establishing a boundary between two consecutive phases; a reference signal supplying an input to said DLL, said reference signal being substantially equal to at least one of said plurality of delay line outputs; and buffer circuitry, having a plurality of inputs corresponding to said plurality of delay line outputs, said buffer circuitry also having a plurality of outputs, each output establishing said boundary between two consecutive phases, said buffer circuitry configured to combine at least one of said plurality of delay line outputs with said reference signal such that error is averaged across at least two of said phases established by said plurality of buffer circuitry outputs.
Claim 2
Independent Claim
135 words
A system for clocking in an integrated circuit, comprising: a delay locked loop (DLL) having a plurality of delay lines, each delay line having an output, each output establishing a boundary between two consecutive phases; a reference signal supplying an input to said DLL, said reference signal being substantially equal to at least one of said plurality of delay line outputs; and buffer circuitry, having a plurality of inputs corresponding to said plurality of delay line outputs, said buffer circuitry also having a plurality of outputs, each output establishing said boundary between two consecutive phases, said buffer circuitry configured to combine at least one of said plurality of delay line outputs with said reference signal such that error is averaged across at least two of said phases established by said plurality of buffer circuitry outputs.
Claim 3
Dependent Claim
32 words
The system of claim 1, wherein said combining circuitry further comprises two inverters having a common output, said two inverters configured to engage in a drive fight during a definable time period.
Claim 4
Dependent Claim
30 words
The system of claim 1, wherein said definable time period includes a time period defined by the operation of an early representation of said reference signal and said reference signal.
Claim 5
Dependent Claim
13 words
The system of claim 1, wherein said DLL produces a quadrature clock output.
Claim 6
Dependent Claim
14 words
The system of claim 1, wherein said error is present in said reference signal.
Claim 7
Dependent Claim
21 words
The system of claim 1, wherein said error is present in at least one of said plurality of delay line outputs.
Claim 8
Independent Claim
117 words
A method for clocking in a delay locked loop (DLL), said DLL including a plurality of delay lines, each delay line having an output, each output establishing a boundary between two consecutive phases, the method comprising the steps of: receiving in said DDL a reference signal; supplying each of said plurality of delay line outputs to a corresponding input of buffering circuitry, said buffering circuitry also having a plurality of outputs, each output establishing said boundary between two consecutive phases; and combining in said buffering circuitry said reference signal and at least one of said plurality of delay line outputs, whereby error is averaged over at least two of said phases established by said buffering circuitry outputs.
Claim 9
Independent Claim
117 words
A method for clocking in a delay locked loop (DLL), said DLL including a plurality of delay lines, each delay line having an output, each output establishing a boundary between two consecutive phases, the method comprising the steps of: receiving in said DDL a reference signal; supplying each of said plurality of delay line outputs to a corresponding input of buffering circuitry, said buffering circuitry also having a plurality of outputs, each output establishing said boundary between two consecutive phases; and combining in said buffering circuitry said reference signal and at least one of said plurality of delay line outputs, whereby error is averaged over at least two of said phases established by said buffering circuitry outputs.
Claim 10
Dependent Claim
13 words
The method of claim 7, wherein said DLL produces a quadrature clock output.
Claim 11
Dependent Claim
14 words
The method of claim 7, wherein said error is present in said reference signal.
Claim 12
Dependent Claim
21 words
The method of claim 7, wherein said error is present in at least one of said plurality of delay line outputs.
Claim 13
Dependent Claim
23 words
The method of claim 7, wherein said at least one of said plurality of delay line outputs is substantially equal said reference signal.
Claim 14
Dependent Claim
40 words
The method of claim 7, wherein said combining step further includes the step of operating, during a definable time period, two inverters having a common output, said two inverters configured to drive fight each other during a definable time period.
Claim 15
Dependent Claim
28 words
The method of claim 7, further comprising the step of using an early version of said reference signal and said reference signal to establish a definable time period.
Claim 16
Independent Claim
124 words
A method for reducing error in a delay locked loop (DLL), said DLL having a plurality of delay lines, each delay line having an output, each output establishing a boundary between two consecutive phases, each output supplied to a corresponding input of buffering circuitry, said buffering circuitry also having a plurality of outputs, each output establishing said boundary between two consecutive phases, the method comprising the step of averaging an error that is represented in one of said plurality of delay line outputs, which is substantially equal to said reference signal over at least two of said phases established by said plurality of outputs of said buffering circuitry by combining, in said buffering circuitry, a reference signal with one of said delay line outputs.
Claim 17
Independent Claim
124 words
A method for reducing error in a delay locked loop (DLL), said DLL having a plurality of delay lines, each delay line having an output, each output establishing a boundary between two consecutive phases, each output supplied to a corresponding input of buffering circuitry, said buffering circuitry also having a plurality of outputs, each output establishing said boundary between two consecutive phases, the method comprising the step of averaging an error that is represented in one of said plurality of delay line outputs, which is substantially equal to said reference signal over at least two of said phases established by said plurality of outputs of said buffering circuitry by combining, in said buffering circuitry, a reference signal with one of said delay line outputs.
Claim 18
Dependent Claim
13 words
The method of claim 14, wherein said DLL produces a quadrature clock output.
Claim 19
Dependent Claim
14 words
The method of claim 14, wherein said error is present in said reference signal.
Claim 20
Dependent Claim
20 words
The method of claim 14, wherein said error is present in at least one of said plurality of DLL outputs.
Claim 21
Dependent Claim
40 words
The method of claim 14, wherein said averaging step further includes the step of operating, during a definable time period, two inverters having a common output, said two inverters configured to drive fight each other during a definable time period.
Claim 22
Dependent Claim
28 words
The method of claim 14, further comprising the step of using an early version of said reference signal and said reference signal to establish a definable time period.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-10 | 2004-04-10 | 2004-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-10 | 2008-04-10 | 2008-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-10 | 2012-04-10 | 2012-10-10 | $7700.00 | Window Closed / Lapsed |