US5420531A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sub-nanosecond calibrated delay line structure
Assignee: Hewlett Packard Development Co LP
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Filing: 1993-09-10
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Granted: 1995-05-30
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Expires: 2013-09-10
Abstract
Abstract Disclosed is a digital phase-locked loop circuit which provides a control signal (332, 334) for a delay circuit (304, 306, 308, 310) within the feedback path of the phase-locked loop. The circuit has a first series of delay circuits (304, 306, 308, 310), which have an incremental control signal input (332, 334), to delay an input clock signal (302) to provide the D input (311) to a D flip flop (312). The input clock signal (302) is also connected to a second series of delay circuits (314, 316, 318, 320, 322). The output of this second series (314, 316, 318, 320, 322) is connected to the clock input (323) of the D flip flop (312). The voltage controlled delay signal input for the second series of delay circuits (314, 316, 318, 320, 322) is supplied by a reference control signal (124, 126). The output of the D flip flop (312) is passed through a resistor-capacitor filtering circuit (324, 325) and fed back to the first series of delay circuits (304, 306, 308, 310) as the incremental control signal. The delay through the first series of circuits is incrementally larger than the delay through the second, reference, series of delay circuits.
Inventors
- 👤 Gary D. Wetlaufer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:20
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
208 words
A circuit for creating an integrated circuit manufacturing process independent analog delay control signal within a single integrated circuit, said signal being used to delay a target signal within said integrated circuit, said circuit comprising: an analog reference circuit for generating an analog reference signal; a first delay circuit having an input connected to an input clock signal and having a controlled delay input connected to said analog delay control signal, wherein said first delay circuit delays said input clock signal to provide a first delayed clock signal as an output; a second delay circuit having an input connected to said input clock signal and a controlled delay input connected to said analog reference signal wherein said second delay circuit delays said input clock signal to provide a second delayed clock signal as an output; a mixing circuit having a first input connected to said first delayed clock signal and having a second input connected to said second delayed clock signal wherein said mixing circuit combines said first delayed clock signal and said second delayed clock signal to create said analog delay control signal; wherein said analog reference circuit, said first delay circuit, said second delay circuit, and said mixing circuit are fabricated within a single integrated circuit.
Claim 2
Dependent Claim
208 words
A circuit for creating an integrated circuit manufacturing process independent analog delay control signal within a single integrated circuit, said signal being used to delay a target signal within said integrated circuit, said circuit comprising: an analog reference circuit for generating an analog reference signal; a first delay circuit having an input connected to an input clock signal and having a controlled delay input connected to said analog delay control signal, wherein said first delay circuit delays said input clock signal to provide a first delayed clock signal as an output; a second delay circuit having an input connected to said input clock signal and a controlled delay input connected to said analog reference signal wherein said second delay circuit delays said input clock signal to provide a second delayed clock signal as an output; a mixing circuit having a first input connected to said first delayed clock signal and having a second input connected to said second delayed clock signal wherein said mixing circuit combines said first delayed clock signal and said second delayed clock signal to create said analog delay control signal; wherein said analog reference circuit, said first delay circuit, said second delay circuit, and said mixing circuit are fabricated within a single integrated circuit.
Claim 3
Dependent Claim
77 words
The digital circuit of claim 1 wherein said first delay circuit comprises a first plurality of delay gates connected in series, each of said first plurality of delay gates having said delay control signal connected to a controlled delay input thereof, and wherein said second delay circuit comprises a second plurality of delay gates connected in series, each of said second plurality of delay gates having said analog reference signal connected to a controlled delay input thereof.
Claim 4
Dependent Claim
133 words
The digital circuit of claim 1 wherein said analog reference circuit comprises: a first delay circuit having an input connected to said input clock signal and having a controlled delay input connected to said analog reference signal, wherein said first delay circuit delays said input clock signal to provide a first reference delayed clock signal as an output; an inverter circuit having an input connected to said input clock signal to provide a second reference delayed clock signal as an output; a mixing circuit having a first input connected to said first reference delayed clock signal and having a second input connected to said second reference delayed clock signal wherein said mixing circuit combines said first reference delayed clock signal and said second reference delayed clock signal to create said analog reference signal.
References Cited (Backward Citations)
US5101117A
Cited
US5216302A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-29 | 1998-11-28 | 1999-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-29 | 2002-11-28 | 2003-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-29 | 2006-11-28 | 2007-05-30 | $7700.00 | Window Closed / Lapsed |