US5638010A — Digitally controlled oscillator for a phase-locke…

Claim 1

Independent Claim 130 words

A digitally controlled oscillator, comprising: a clock signal generator having a first input for receiving a frequency control signal, a second input for receiving a master clock signal and an output providing an output clock signal with clock pulses occurring at an average frequency proportional to the frequency control signal; and a time measuring circuit having an input connected to receive the output clock signal, and an output providing, for each clock pulse received from the output clock signal, a measure of a time period between an arrival time of a clock pulse of an imaginary ideal clock signal having a uniform period and a frequency equal to the average frequency of the output clock signal and an arrival time of the clock pulse received from the output clock signal.

Claim 2

Dependent Claim 130 words

A digitally controlled oscillator, comprising: a clock signal generator having a first input for receiving a frequency control signal, a second input for receiving a master clock signal and an output providing an output clock signal with clock pulses occurring at an average frequency proportional to the frequency control signal; and a time measuring circuit having an input connected to receive the output clock signal, and an output providing, for each clock pulse received from the output clock signal, a measure of a time period between an arrival time of a clock pulse of an imaginary ideal clock signal having a uniform period and a frequency equal to the average frequency of the output clock signal and an arrival time of the clock pulse received from the output clock signal.

Claim 3

Dependent Claim 124 words

The digitally controlled oscillator of claim 1, wherein the clock signal generator comprises a modulo accumulator having an input receiving the frequency control signal and an output which increments according to the frequency control signal and according to the master clock signal, and which periodically wraps when the output of the modulo accumulator exceeds a threshold to generate the output clock signal at the output of the clock signal generator; and wherein the time measuring circuit comprises a latch that samples lower bits of the output of the modulo accumulator when the modulo accumulator wraps as indicated by the output clock signal and before any subsequent pulse of the master clock signal to provide an output indicative of the measure of the time period.

Claim 4

Dependent Claim 96 words

The digitally controlled oscillator of claim 2, wherein the modulo accumulator comprises: an adder having an input connected to receive the frequency control signal and a second input and an output providing the sum of the first and second inputs; and a first latch having an input connected to the output of the adder and an output connected to the second input of the adder and which latches the output of the adder on pulses of the master clock signal, wherein a most significant bit of the output of the latch provides the output clock signal.

Claim 5

Dependent Claim 71 words

The digitally controlled oscillator of claim 3, further comprising: a second latch connected to receive the frequency control signal and which latches according to a delayed master clock signal; and a divider having a first input connected to the output of the time measuring circuit and a second input connected to the output of the second latch and an output providing a quotient of the first input to the second input.

Claim 6

Dependent Claim 48 words

The digitally controlled oscillator of claim 2, further comprising: a divider having a first input connected to receive the frequency control signal and a second input connected to receive the output of the latch and an output providing a quotient of the first input to the second input.

Claim 7

Dependent Claim 49 words

The digitally controlled oscillator of claim 1, further comprising: a divider having a first input connected to receive the frequency control signal and a second input connected to receive the measure of the time period and an output providing a quotient of the first input to the second input.

Claim 8

Dependent Claim 13 words

The digitally controlled oscillator of claim 1 embodied in a digital phase-locked loop.

Claim 9

Dependent Claim 187 words

A digitally controlled oscillator, comprising: a modulo accumulator having a first input for receiving a frequency control signal and a second input for receiving a master clock signal, and an output which increments according to the frequency control signal and according to the master clock signal, and which periodically wraps when the output exceeds a threshold to generate an output clock signal with pulses occurring at an average frequency proportional to the frequency control signal; and a first latch having an input connected to receive lower bits of the output of the modulo accumulator and a latch input connected to receive the output clock signal, and an output which provides a sample of lower bits of the output of the modulo accumulator when the modulo accumulator wraps and before any subsequent pulse of the master clock signal to provide a measure of time between an arrival time of a clock pulse of an imaginary ideal clock signal having a uniform period and a frequency equal to the average frequency of the output clock signal and an arrival time of a clock pulse in the output clock signal.

Claim 10

Dependent Claim 187 words

A digitally controlled oscillator, comprising: a modulo accumulator having a first input for receiving a frequency control signal and a second input for receiving a master clock signal, and an output which increments according to the frequency control signal and according to the master clock signal, and which periodically wraps when the output exceeds a threshold to generate an output clock signal with pulses occurring at an average frequency proportional to the frequency control signal; and a first latch having an input connected to receive lower bits of the output of the modulo accumulator and a latch input connected to receive the output clock signal, and an output which provides a sample of lower bits of the output of the modulo accumulator when the modulo accumulator wraps and before any subsequent pulse of the master clock signal to provide a measure of time between an arrival time of a clock pulse of an imaginary ideal clock signal having a uniform period and a frequency equal to the average frequency of the output clock signal and an arrival time of a clock pulse in the output clock signal.

Claim 11

Dependent Claim 97 words

The digitally controlled oscillator of claim 8, wherein the modulo accumulator comprises: an adder having an input connected to receive the frequency control signal and a second input and an output providing the sum of the first and second inputs; and a second latch having an input connected to the output of the adder and an output connected to the second input of the adder and which latches the output of the adder on pulses of the master clock signal, wherein a most significant bit of the output of the second latch provides the output clock signal.

Claim 12

Dependent Claim 70 words

The digitally controlled oscillator of claim 9, further comprising: a third latch connected to receive the frequency control signal and which latches according to a delayed master clock signal; and a divider having a first input connected to the output of the first latch and a second input connected to the output of the third latch and an output providing a quotient of the first input to the second input.

Claim 13

Dependent Claim 47 words

The digitally controlled oscillator of claim 8, further comprising: a divider having a first input connected to receive the frequency control signal and a second input connected to receive the measured time period and an output providing a quotient of the first input to the second input.

Claim 14

Dependent Claim 109 words

The digitally controlled oscillator of claim 8, embodied in a digital phase-locked loop for generating an output clock signal having an average frequency substantially higher than an input clock signal, comprising: a phase detector having a first input connected to receive the input clock signal and a second input connected to receive the output clock signal from the digitally controlled oscillator and an output providing a signal indicative of a measure of a difference in phase of the first and second inputs; and a loop filter connected to receive the output of the phase detector and having an output providing the frequency control signal to the digitally controlled oscillator.

Claim 15

Dependent Claim 172 words

The digitally controlled oscillator of claim 12, wherein the digital phase-locked loop is embodied in a digital interpolation filter for interpolating input data received at a rate defined by the input clock signal to generate an output filtered signal at a rate defined by the output clock signal, comprising: an interpolator having a first input for receiving the output clock signal of the digitally controlled oscillator and a second input for receiving the input data and an output providing a signal indicative of interpolated input data, at time intervals according to the output clock signal; and a correction circuit having an input connected to receive a first interpolated output from a first time and a second interpolated output from a second time and a second input connected to receive the measure of the time period from the digitally controlled oscillator and an output providing the output filtered signal indicative of a result of a corrective function applied to the first and second interpolated outputs according to the measure of the time period.

Claim 16

Dependent Claim 51 words

The digitally controlled oscillator of claim 13, wherein the corrective function is an extrapolation function and the output filtered signal is the sum of the second interpolated output and the product of the measure of the time period and the difference between the second interpolated output and the first interpolated output.

Claim 17

Dependent Claim 85 words

The digitally controlled oscillator of claim 13 embodied in a circuit for converting the input data to an analog signal, comprising: a noise shaper, having an input connected to receive the output of the digital interpolation filter at a rate defined by the output clock signal of the digitally controlled oscillator, and an output which provides a noise-shaped signal; a digital-to-analog converter, having an input connected to receive the output of the noise-shaper and an output providing the analog signal according to the noise-shaped signal.

Claim 18

Dependent Claim 111 words

The digitally controlled oscillator of claim 12, embodied in a digital decimation filter for decimating input data received at a rate defined by the master clock signal to provide an output decimated signal at a rate related to the phase-locked output clock signal, comprising: a correction circuit which receives the input data according to the master clock signal and generates a corrected output from the input data for each clock pulse of the phase-locked output clock signal; and a decimator having an input connected to receive the corrected output from the correction circuit at a rate related to the phase-locked output clock signal and an output providing the output decimated signal.

Claim 19

Dependent Claim 27 words

The digitally controlled oscillator of claim 16, wherein the correction circuit performs backward interpolation according to the measure of the time period and two adjacent input values.

Claim 20

Dependent Claim 38 words

The digitally controlled oscillator of claim 17, further comprising means for normalizing the measure of the time period wherein the measure of the time period used by the correction circuit is the normalized measure of the time period.

Claim 21

Dependent Claim 60 words

The digitally controlled oscillator of claim 13, embodied in a sample rate converter for converting the input data to a sequence of output samples at an output sampling rate, comprising: a decimation filter having an input for receiving the output filtered signal and an output providing a decimated output filtered signal at a rate according to the output sampling rate.

Claim 22

Dependent Claim 152 words

A process for generating a digitally controlled output clock signal having an average frequency defined by a frequency control signal, and a measure of a time period between pulses of the output clock signal and an imaginary ideal clock signal having a uniform period and a frequency equal to the average frequency of the output clock signal, comprising the steps of: generating a periodically overflowing ramp signal, having a most significant bit providing the output clock signal, and lower bits using an accumulator having an input connected to receive the frequency control signal and an output providing a signal indicative of an accumulation of the frequency control signal in response to pulses of a master clock signal; and sampling the lower bits of the output of the accumulator in response to a transition in the most significant bit of the accumulator and before a subsequent pulse of the master clock signal occurs.

Claim 23

Dependent Claim 152 words

A process for generating a digitally controlled output clock signal having an average frequency defined by a frequency control signal, and a measure of a time period between pulses of the output clock signal and an imaginary ideal clock signal having a uniform period and a frequency equal to the average frequency of the output clock signal, comprising the steps of: generating a periodically overflowing ramp signal, having a most significant bit providing the output clock signal, and lower bits using an accumulator having an input connected to receive the frequency control signal and an output providing a signal indicative of an accumulation of the frequency control signal in response to pulses of a master clock signal; and sampling the lower bits of the output of the accumulator in response to a transition in the most significant bit of the accumulator and before a subsequent pulse of the master clock signal occurs.

Claim 24

Dependent Claim 62 words

The process of claim 20, wherein the step of generating comprises the steps of: accumulating the frequency control signal and a sum for each pulse of the master clock signal; and sampling the accumulated frequency control signal for each pulse of the master clock signal to provide the sum, wherein a most significant bit of the sum provides the output clock signal.

Claim 25

Dependent Claim 28 words

The process of claim 21, further comprising the step of dividing the measure of the time period by the frequency control signal to provide a normalized residue signal.

Claim 26

Dependent Claim 28 words

The process of claim 20, further comprising the step of dividing the measure of the time period by the frequency control signal to provide a normalized residue signal.

Claim 27

Dependent Claim 76 words

The process of claim 20, used in a process for making the output clock signal phase-locked to and having an average frequency substantially higher than an input clock signal, comprising the steps of: determining a phase difference between the input clock signal and the output clock signal; and filtering the phase difference to provide the frequency control signal used in the step of generating to phase lock the output clock signal to the input clock signal.

Claim 28

Dependent Claim 103 words

The process of claim 24, used in a process for interpolating input data received at a rate defined by the input clock signal to generate an output filtered signal at a rate defined by the phase-locked output clock signal, comprising the steps of: oversampling the input data at a rate defined by the phase-locked output clock signal to provide a sample for each pulse of the phase-locked output clock signal; and correcting each sample of the oversampled input signal according to the measure of the time period of the associated pulse of the phase-locked output clock signal to provide the output filtered signal.

Claim 29

Dependent Claim 44 words

The process of claim 25, wherein the step of correcting includes the step of extrapolating the oversampled input signal using at least two adjacent outputs of the output filtered signal for each sample and the measure of the time period associated with the sample.

Claim 30

Dependent Claim 33 words

The process of claim 25, used in a process for converting the input data to an analog signal, comprising: noise-shaping the output filtered signal; and converting the noise-shaped signal into the analog signal.

Claim 31

Dependent Claim 127 words

The process of claim 24, used in a process for decimating input data received at a rate defined by the master clock signal, wherein the master clock signal is the input clock signal to the step of determining a phase difference, to provide an output decimated signal at a rate related to the phase-locked output clock signal, comprising: correcting each value of the input data using the measure of the time period for each pulse of the phase-locked clock signal to provide corrected data with values corresponding to sample times of the phase-locked output clock signal; and decimating the corrected signal using a decimation filter by reading each corrected value of the input data at a rate related to the frequency of the phase-locked output clock signal.

Claim 32

Dependent Claim 31 words

The process of claim 28, wherein the step of correcting includes performing backwards interpolation of at least two sequential values of the input data and the measure of the time period.

Claim 33

Dependent Claim 21 words

The process of claim 29, wherein the step of correcting comprises a step of normalizing the measure of the time period.

Claim 34

Dependent Claim 39 words

The process of claim 25, used in a process for converting the input data to a sequence of output samples having an output sampling rate, comprising the step of decimating the output filtered signal at the output sampling rate.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2000-06-09	2000-12-09	2001-06-10	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2004-06-09	2004-12-09	2005-06-10	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2008-06-09	2008-12-09	2009-06-10	$7700.00	Window Closed / Lapsed

Digitally controlled oscillator for a phase-locked loop providing a residue signal for use in continuously variable interpolation and decimation filters

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag