Direct digital to digital sampling rate conversion, method and apparatus

Claim 3

The method of claim 1 wherein said interpolating steps comprises linearly interpolating said increased signal.

Claim 4

The method of claim 2 wherein said interpoating step interpolates a pair of increased signals.

Claim 5

A direct digital to digital sampling rate conversion apparatus for converting an input digital signal having a first sampling ratee to an output digital signal having a second sampling rate, said apparatus comprising: a timing signal generating means for producing timing signals at said first rate, at an increased rate which is an integral multiple of said first rate, and at said second rate; rate multiplication means having a first storage means with a discrete number of storage locations for receiving said input digital signal, a second storage means for storing a predetermined number of coefficients, said second storage means having a number of storage locations at least equal to said discrete number times said integral multiple; a multiplier means for generating a plurality of multiplied signals by multiplying select values in said first storage means with values in said second storage means; and an accumulator means for summing said multiplied signals; and wherein said rate multiplication means receives timing signals at said first rate, and at said increased rate and produces an increased digital signal at said increased rate in accordance with: ##EQU10## where: RAM(I) is the value of the first storage means in the Ith storage location; ROM(K * I+Offset) is the value of the second storage means in the K * I+Offset storage location; K is said integral multiple; Offset is a number from 0 to K-1; N is the discrete number of storage locations; and interpolating means for receiving said increased signal and said timing signal at said second rate and for interpolating said increased signal to produce said output signal.

Claim 6

A direct digital to digital sampling rate conversion apparatus for converting an input digital signal having a first sampling ratee to an output digital signal having a second sampling rate, said apparatus comprising: a timing signal generating means for producing timing signals at said first rate, at an increased rate which is an integral multiple of said first rate, and at said second rate; rate multiplication means having a first storage means with a discrete number of storage locations for receiving said input digital signal, a second storage means for storing a predetermined number of coefficients, said second storage means having a number of storage locations at least equal to said discrete number times said integral multiple; a multiplier means for generating a plurality of multiplied signals by multiplying select values in said first storage means with values in said second storage means; and an accumulator means for summing said multiplied signals; and wherein said rate multiplication means receives timing signals at said first rate, and at said increased rate and produces an increased digital signal at said increased rate in accordance with: ##EQU10## where: RAM(I) is the value of the first storage means in the Ith storage location; ROM(K * I+Offset) is the value of the second storage means in the K * I+Offset storage location; K is said integral multiple; Offset is a number from 0 to K-1; N is the discrete number of storage locations; and interpolating means for receiving said increased signal and said timing signal at said second rate and for interpolating said increased signal to produce said output signal.

Claim 7

The apparatus of claim 4 wherein said apparatus further comprises counter means for receiving and counting said timing signal at said second rate; table means for storing a plurality of values of the relative positions of the second rate timing signals to said increased rate timing signals, and for storing a plurality of storage address values, one storage address value for each value of the relative position; said table means in response to the count in said counter means, supplying a stored value of the relative position to said interpolating means, and supplying a storage address value to said rate multiplication means.

Claim 8

The apparatus of claim 4 wherein said first rate and said second rate are in a variable ratio.

Claim 9

The apparatus of claim 4 wherein said interpolating means is an Nth order N-polynomial interpolator.

Claim 10

The apparatus of claim 4 wherein said first rate and second rate are predetermined.

Claim 11

The apparatus of claim 4 wherein said rate multiplication means comprises a plurality of rate multipliers.

Claim 12

The apparatus of claim 4 wherein said rate multiplication means further comprises: filter cycle means for selecting an input signal in said first storage means for multiplication by a coefficient in said second storage means.

Claim 13

The apparatus of claim 7 wherein N equals 1.

Claim 14

The apparatus of claim 10 wherein said first storage means is a RAM.

Claim 15

The apparatus of claim 5 wherein said interpolating means receives said timing signal at said second rate and receives a pair of increased signals and produces said output signal therefrom.