Analog/digital converter configuration with sigma-delta modulators

Claim 2

Analog/digital converter configuration, comprising: i sigma-delta modulators each having an output and being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate, said sigma-delta modulators having input circuits with amplification factors and i being a positive integer, i amplifiers each being connected to the input circuit of a respective one of said sigma-delta modulators, i first sampling rate reducers each having an input and an output and each being connected to the output of a respective one of said sigma-delta modulators, i damping elements each having an input and an output and each being connected to the output of a respective one of said first sampling rate reducers, each of said damping elements having a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a respective one of said sigma-delta modulators, a priority logic circuit having an input and an output, said priority logic circuit being connected to the output of said damping elements, a second sampling rate reducer connected to the output of said priority logic circuit, and said second sampling rate reducer having an output, said priority logic circuit switching a signal from said first sampling rate reducers to said output after evaluation of signals from said first sampling rate reducers.

Claim 3

Analog/digital converter according to claim 1, wherein each two adjacent sigma-delta modulators are connected to one another through a respective one of said amplifiers, and all of said amplifiers have the same amplification factor.

Claim 4

Analog/digital converter according to claim 2, wherein the amplification factor of said amplifiers is a power of two.

Claim 5

Analog/digital converter according to claim 1, wherein said amplifiers to the input of said sigma-delta modulators are connected in parallel and have different amplification factors.

Claim 6

Analog/digital converter according to claim 4, wherein the amplification factors of said amplifiers are powers of two.

Claim 7

Analog/digital converter according to claim 1, wherein said amplifiers have amplification factors, said priority logic circuit compares signals from said first sampling rate reducers with threshold values each being associated with said first sampling rate reducers, and one of said first sampling rate reducers having a signal not exceeding the threshold value and being connected to one of said amplifiers having the highest amplification factor, being switched through to said output by said priority logic circuit.

Claim 8

Analog/digital converter according to claim 6, wherein said amplifiers each have a modulation limit, and the threshold values are each equivalent to a modulation of a respective associated amplifier within the modulation limit of said respective amplifier.

Claim 9

Analog/digital converter according to claim 6, wherein when a threshold value is exceeded, said priority logic circuit performs a switchover from one of said sampling rate reducers to another in a delayed manner if one of said amplifiers associated with one of said first sampling rate reducers has a higher amplification factor than said amplifier associated with the other of said sampling rate reducers; and performs the switchover without delay if one of said amplifiers associated with one of said first sampling rate reducers has a lower amplification factor than said amplifier associated with the other of said sampling rate reducers.

Claim 10

Analog/digital converter configuration, comprising: a plurality of sigma-delta modulators being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate, said sigma-delta modulators having input circuits with amplification factors and outputs, a plurality of amplifiers each being connected to the input circuit of a respective one of said sigma-delta modulators, a plurality of first sampling rate reducers each having an input and an output and each being connected to the output of a respective one of said sigma-delta modulators, a plurality of damping elements each having an input and an output and each being connected to the output of a respective one of said first sampling rate reducers, each of said damping elements having a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a respective one of said sigma-delta modulators, a priority logic circuit having an input and an output, said priority logic circuit being connected to the output of said damping elements, a second sampling rate reducer connected to the output of said priority logic circuit, and said second sampling rate reducer having an output, said priority logic circuit switching a signal from said first sampling rate reducers to said output after evaluation of signals from said first sampling rate reducers.

Claim 11

Analog/digital converter configuration, comprising: a plurality of sigma-delta modulators being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate, said sigma-delta modulators having input circuits with amplification factors and outputs, a plurality of amplifiers each being connected to the input circuit of a respective one of said sigma-delta modulators, a plurality of first sampling rate reducers each having an input and an output and each being connected to the output of a respective one of said sigma-delta modulators, a plurality of damping elements each having an input and an output and each being connected to the output of a respective one of said first sampling rate reducers, each of said damping elements having a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a respective one of said sigma-delta modulators, a priority logic circuit having an input and an output, said priority logic circuit being connected to the output of said damping elements, a second sampling rate reducer connected to the output of said priority logic circuit, and said second sampling rate reducer having an output, said priority logic circuit switching a signal from said first sampling rate reducers to said output after evaluation of signals from said first sampling rate reducers.

Claim 12

Analog/digital converter configuration, comprising: i sigma-delta modulators each having an output and each being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate, said sigma-delta modulators having input circuits with amplification factors and i being a positive integer, i amplifiers each connected to the input circuit of a respective one of said sigma-delta modulators, i first sampling rate reducers each having an input and an output and each being connected to the output of a respective one of said sigma-delta modulators, means for damping with a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a respective one of said sigma-delta modulators, a priority logic circuit having an input and an output, said priority logic circuit being connected to the output of said first sampling rate reducers, a second sampling rate reducer connected to the output of said priority logic circuit, and said second sampling rate reducer having an output, said priority logic circuit switching a signal from said first sampling rate reducers to said output after evaluation of signals from said first sampling rate reducers.

Claim 13

Analog/digital converter configuration, comprising: i sigma-delta modulators each having an output and each being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate, said sigma-delta modulators having input circuits with amplification factors and i being a positive integer, i amplifiers each connected to the input circuit of a respective one of said sigma-delta modulators, i first sampling rate reducers each having an input and an output and each being connected to the output of a respective one of said sigma-delta modulators, means for damping with a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a respective one of said sigma-delta modulators, a priority logic circuit having an input and an output, said priority logic circuit being connected to the output of said first sampling rate reducers, a second sampling rate reducer connected to the output of said priority logic circuit, and said second sampling rate reducer having an output, said priority logic circuit switching a signal from said first sampling rate reducers to said output after evaluation of signals from said first sampling rate reducers.