US4954824A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sample rate conversion system having interpolation function with phase locked clock
Assignee: Toshiba Corp
•
Filing: 1988-09-15
•
Granted: 1990-09-04
•
Expires: 2008-09-15
Abstract
Abstract A sample rate conversion circuit converts first digital data processed by a first clock signal having a first frequency into digital data processed by a second clock signal having a second frequency. A ring oscillator has a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop so as to output polyphase delay clock signals and a predetermined self-excited oscillation signal. A phase-locking circuit applies a control voltage corresponding to a phase difference between the first clock signal and the self-excited oscillation signal to each of the voltage-controlled gate delay elements so as to phase-lock the first clock signal with the self-excited oscillation signal output from the ring oscillator. A latch circuit latches the polyphase delay clock signals output from the ring oscillator in accordance with the second clock signal. An interpolation coefficient generator generates an interpolation coefficient corresponding to phase data between the first and second clock signals in accordance with the polyphase delay clock signals latched by the latch circuit. An interpolating circuit interpolates two adjacent data of the first digital data by using the interpolation coefficient generated by the interpolation coefficient generator and outputting the interpolated data as the second digital data.
Inventors
- 👤 Masahiro Yamada
- 👤 Kiyoyuki Kawai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:12
CPC Classifications
H; H03; H03K; H03K7/00; H03K7/06; H03H; H03H17/00; H03H17/02; H03H17/06; H03H17/0621; H03H17/0628; G; G01; G01R; G01R25/00
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
207 words
A sample rate conversion circuit for converting first digital data processed by a first clock signal having a first frequency into digital data processed by a second clock signal having a second frequency, comprising: ring oscillator means, having a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop, for outputting polyphase delay clock signals and a predetermined self-excited oscillation signal; phase-locking means for applying a control voltage corresponding to a phase difference between the first clock signal and the self-excited oscillation signal to each of said voltage-controlled gate delay elements so as to phase-lock the first clock signal with the self-excited oscillation signal output from said ring oscillator means; latch means for latching the polyphase delay clock signals output from said ring oscillator means in accordance with the second clock signal; interpolation coefficient generating means for generating an interpolation coefficient corresponding to phase data between the first and second clock signals in accordance with the polyphase delay clock signals latched by said latch means; and interpolating means for interpolating two adjacent data of the first digital data by using the interpolation coefficient generated by said interpolation coefficient generating means and outputting the interpolated data as the second digital data.
Claim 2
Dependent Claim
207 words
A sample rate conversion circuit for converting first digital data processed by a first clock signal having a first frequency into digital data processed by a second clock signal having a second frequency, comprising: ring oscillator means, having a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop, for outputting polyphase delay clock signals and a predetermined self-excited oscillation signal; phase-locking means for applying a control voltage corresponding to a phase difference between the first clock signal and the self-excited oscillation signal to each of said voltage-controlled gate delay elements so as to phase-lock the first clock signal with the self-excited oscillation signal output from said ring oscillator means; latch means for latching the polyphase delay clock signals output from said ring oscillator means in accordance with the second clock signal; interpolation coefficient generating means for generating an interpolation coefficient corresponding to phase data between the first and second clock signals in accordance with the polyphase delay clock signals latched by said latch means; and interpolating means for interpolating two adjacent data of the first digital data by using the interpolation coefficient generated by said interpolation coefficient generating means and outputting the interpolated data as the second digital data.
Claim 3
Dependent Claim
48 words
A circuit according to claim 1, wherein said phase-locking means includes a phase comparator for comparing a phase of the first clock signal with that of the self-excited oscillation signal output from said ring oscillator means, and a loop filter for receiving an output from said phase comparator.
Claim 4
Dependent Claim
39 words
A circuit according to claim 1, wherein said interpolation coefficient generating means includes a conversion table circuit for outputting first and second interpolation coefficients k and (1-k) corresponding to the phase data between the first and second clock signals.
Claim 5
Dependent Claim
58 words
A circuit according to claim 3, wherein said interpolating means includes a first multiplier for multiplying one of the two adjacent data by the first interpolation coefficient k, a second multiplier for multiplying the other of the two adjacent data by the second interpolation coefficient (1-k), and an adder for adding outputs from said first and second multipliers.
Claim 6
Dependent Claim
49 words
A circuit according to claim 1, wherein said interpolation coefficient generating means includes means for providing the phase data by determining a relative phase between the first and second clock signals in accordance with a specific pattern represented by the polyphase delay clock signal latched by said latch means.
Claim 7
Dependent Claim
67 words
A circuit according to claim 1, wherein said ring oscillator means outputs the self-excited oscillation signal having frequency f=1/2nΔt (where n is the number of the voltage-controlled gate delay elements) when the predetermined number of said voltage-controlled gate delay elements is set to be Δt, and outputs the polyphase delay clock having a phase relationship obtained by dividing one period of the first clock signal by 2n.
Claim 8
Dependent Claim
36 words
A circuit according to claim 1, further comprising data phase-locking means for lock-phasing the two adjacent data of the first digital data with a specific one of the polyphase clock signals from said ring oscillator means.
Claim 9
Dependent Claim
32 words
A circuit according to claim 7, wherein said data phase-locking means includes first and second latches for respectively latching the two adjacent data by using one of the polyphase delay clock signals.
Claim 10
Dependent Claim
195 words
A sample rate conversion system comprising: a first digital data processing system for sampling input data in accordance with a first clock signal having a first frequency; a second digital data processing system for sampling input data in accordance with a second clock signal having a second frequency; and sample rate converting means for receiving the data sampled by said first digital data processing system, converting the data into data having a sample rate matched with said second digital data processing system, and outputting the converted data, said sample rate conversion means further comprising: phase-locking oscillation means for outputting polyphase delay clock signals phase-locked with the first clock signal, interpolation coefficient generating means for obtaining phase data between the first and second clock signals by receiving the polyphase delay clock signals output from said phase-locking oscillation means in response to the second clock signal, and generating an interpolation coefficient corresponding to the phase data, and interpolating means for interpolating two adjacent data received from said first digital data processing system in accordance with the interpolation coefficient generated by said interpolation coefficient generating means, and supplying the interpolated data to said second digital data processing system.
Claim 11
Dependent Claim
195 words
A sample rate conversion system comprising: a first digital data processing system for sampling input data in accordance with a first clock signal having a first frequency; a second digital data processing system for sampling input data in accordance with a second clock signal having a second frequency; and sample rate converting means for receiving the data sampled by said first digital data processing system, converting the data into data having a sample rate matched with said second digital data processing system, and outputting the converted data, said sample rate conversion means further comprising: phase-locking oscillation means for outputting polyphase delay clock signals phase-locked with the first clock signal, interpolation coefficient generating means for obtaining phase data between the first and second clock signals by receiving the polyphase delay clock signals output from said phase-locking oscillation means in response to the second clock signal, and generating an interpolation coefficient corresponding to the phase data, and interpolating means for interpolating two adjacent data received from said first digital data processing system in accordance with the interpolation coefficient generated by said interpolation coefficient generating means, and supplying the interpolated data to said second digital data processing system.
Claim 12
Dependent Claim
47 words
A circuit according to claim 9, wherein said phase-locking oscillation means includes ring oscillator means, having a predetermined number of voltage-controlled gate delay elements connected to each other in the form of a loop, for outputting the polyphase delay clock signals and a predetermined self-excited oscillation signal.
Claim 13
Dependent Claim
48 words
A circuit according to claim 10, wherein said phase-locking means includes a phase comparator for comparing a phase of the first clock signal with that of the self-excited oscillation signal output from said ring oscillator means, and a loop filter for receiving an output from said phase comparator.
Claim 14
Dependent Claim
67 words
A circuit according to claim 10, wherein said ring oscillator means outputs the self-excited oscillation signal having frequency f=1/2nΔt (where n is the number of the voltage-controlled gate delay elements) when the predetermined number of said voltage-controlled gate delay elements is set to be Δt, and outputs the polyphase delay clock having a phase relationship obtained by dividing one period of the first clock signal by 2n.
Claim 15
Dependent Claim
36 words
A circuit according to claim 10, further comprising data phase-locking means for lock-phasing the two adjacent data of the first digital data with a specific one of the polyphase clock signals from said ring oscillator means.
Claim 16
Dependent Claim
32 words
A circuit according to claim 13, wherein said data phase-locking means includes first and second latches for respectively latching the two adjacent data by using one of the polyphase delay clock signals.
Claim 17
Dependent Claim
39 words
A circuit according to claim 9, wherein said interpolation coefficient generating means includes a conversion table circuit for outputting first and second interpolation coefficients k and (1-k) corresponding to the phase data between the first and second clock signals.
Claim 18
Dependent Claim
58 words
A circuit according to claim 15, wherein said interpolating means includes a first multiplier for multiplying one of the two adjacent data by the first interpolation coefficient k, a second multiplier for multiplying the other of the two adjacent data by the second interpolation coefficient (1-k), and an adder for adding outputs from said first and second multipliers.
Claim 19
Dependent Claim
49 words
A circuit according to claim 9, wherein said interpolation coefficient generating means includes means for providing the phase data by determining a relative phase between the first and second clock signals in accordance with a specific pattern represented by the polyphase delay clock signal latched by said latch means.
References Cited (Backward Citations)
US4091335A
Cited
JPS57159121A
Cited
US4460890A
Cited
US4513427A
Cited
US4612573A
Cited
US4797845A
Cited
JPS6386932A
Cited
JPS63177619A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |