US4990911A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sampling frequency converter
Assignee: Sony Corp
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Filing: 1989-04-04
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Granted: 1991-02-05
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Expires: 2009-04-04
Abstract
Abstract A relatively simplified sampling frequency converter for use in a format conversion apparatus is operative to convert sampled input data of an input sampling frequency into sampled output data of an output sampling frequency. The converter has an over-sampling circuit for increasing the sampling frequency of the sampled input data by a predetermined factor or coefficient to provide over-sampled data; an output data extractor for periodically extracting data from the over-sampled data in response to a timing pulse having the output sampling frequency; and a controller for controlling the phase of the timing pulse which controls the phase of the sampled output data.
Inventors
- 👤 Tadao Fujita
- 👤 Jun Takayama
- 👤 Takeshi Ninomiya
- 👤 Yoshikazu Kurose
- 👤 Yoshiaki Inaba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:50
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; H; H04; H04N; H04N7/00; H04N7/01; H04N7/0102
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
100 words
A sampling frequency converter for converting sampled input data having an input sampling frequency into sampled output data having a different output sampling frequency, comprising: over-sampling means supplied with said sampled input data for increasing the sampling frequency of said sampled input data by a factor n to provide over-sampled data; means for generating a timing pulse having said output sampling frequency; output data extractor means for periodically extracting data from said over-sampled data in response to said timing pulse; and control means for controlling the timing of said timing pulse to control the phase of said sampled output data.
Claim 2
Dependent Claim
100 words
A sampling frequency converter for converting sampled input data having an input sampling frequency into sampled output data having a different output sampling frequency, comprising: over-sampling means supplied with said sampled input data for increasing the sampling frequency of said sampled input data by a factor n to provide over-sampled data; means for generating a timing pulse having said output sampling frequency; output data extractor means for periodically extracting data from said over-sampled data in response to said timing pulse; and control means for controlling the timing of said timing pulse to control the phase of said sampled output data.
Claim 3
Dependent Claim
49 words
A sampling frequency converter according to claim 1, wherein one of said sampled input and output data is a digital color signal in a digital composite color signal format, and another of said sampled input and output data is a digital color signal in a digital component signal format.
Claim 4
Dependent Claim
49 words
A sampling frequency converter according to claim 1, wherein one of said sampled input and output data is a digital luminance signal in a digital composite color signal format, and another of said sampled input and output data is a digital luminance signal in a digital component signal format.
Claim 5
Dependent Claim
57 words
A sampling frequency converter according to claim 3, wherein said sampled input and output data further include a digital color signal, and wherein said control means controls the timing of said timing pulse in such a manner that a delay imparted to said digital luminance signal becomes equal to a delay imparted to the digital color signal.
Claim 6
Dependent Claim
31 words
A sampling frequency converter according to claim 1, wherein said n equals the ratio of the least common multiple of said input and output sampling frequencies to the input sampling frequency.
Claim 7
Dependent Claim
132 words
A sampling frequency converter according to claim 1, wherein said over-sampling means includes serially connected latch circuits supplied with said sampled input data for latching the same for one sampling period of said sampled input data, multiplier means connected to the output of each of said latch circuits, ROM means connected to each of said multiplier means for storing a plurality of coefficient data which are read out selectively in a predetermined order and supplied to said corresponding multiplier means for multiplying in the latter by the output of said latch circuit, and adder means for adding the outputs of said multiplier means together; and wherein said output extractor means includes an address controller for controlling the read address of said ROM means with the frequency corresponding to said output sampling frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-04 | 1994-08-06 | 1995-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-04 | 1998-08-06 | 1999-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-04 | 2002-08-06 | 2003-02-05 | $7700.00 | Window Closed / Lapsed |