Dual damascene bond pad structure for lowering stress and allowing circuitry under pads

Claim 2

A semiconductor device comprising a bond pad formed over a substrate region including active devices formed thereon, the bond pad including bond pad metal formed within an opening having a lower surface formed of a barrier layer, and within at least one via formed through the lower surface and through a dielectric layer disposed beneath the barrier layer.

Claim 3

The semiconductor device as in claim 1 , further comprising a conductive layer interposed between the substrate region and the dielectric layer.

Claim 4

The semiconductor device as in claim 2 , wherein the bond pad is coupled to the conductive layer through the at least one via.

Claim 5

The semiconductor device as in claim 2 , wherein the conductive layer is coupled to at least one of the active devices.

Claim 6

The semiconductor device as in claim 2 , wherein the conductive layer comprises a patterned film.

Claim 7

The semiconductor device as in claim 1 , wherein the barrier layer comprises TiN.

Claim 8

The semiconductor device as in claim 1 , wherein the barrier layer is formed of a material selected from the group consisting of Ta, Ti, TaN, WSi, WSiN, TaSi and TiSi.

Claim 9

The semiconductor device as in claim 1 , further comprising a conductive wire coupled to a top surface of the bond pad.

Claim 10

The semiconductor device as in claim 1 , further comprising a further barrier layer formed over at least part of the bond pad metal within the bond pad opening.

Claim 11

The semiconductor device as in claim 1 , wherein the bond pad metal comprises one of W, Al, Cu, an aluminum alloy and a copper alloy.

Claim 12

The semiconductor device as in claim 2 , wherein the conductive layer comprises one of W, Al, Cu, an aluminum alloy, and a copper alloy.

Claim 13

A semiconductor device comprising: a) a substrate having a substrate surface; b) active devices formed on the substrate surface including within a first region; c) a lower dielectric layer formed over the active devices including within the first region; d) an upper dielectric layer formed over the lower dielectric layer; e) a barrier layer formed between the upper dielectric layer and the lower dielectric layer at least within the first region; and f) a bond pad formed within an opening formed within the upper dielectric film in the first region and extending down to the barrier layer, the bond pad including a bond pad metal formed within the opening, contacting the barrier layer, and extending downward beneath the barrier layer through at least one via formed through the barrier layer and through the lower dielectric layer in the first region.

Claim 14

A semiconductor device comprising: a) a substrate having a substrate surface; b) active devices formed on the substrate surface including within a first region; c) a lower dielectric layer formed over the active devices including within the first region; d) an upper dielectric layer formed over the lower dielectric layer; e) a barrier layer formed between the upper dielectric layer and the lower dielectric layer at least within the first region; and f) a bond pad formed within an opening formed within the upper dielectric film in the first region and extending down to the barrier layer, the bond pad including a bond pad metal formed within the opening, contacting the barrier layer, and extending downward beneath the barrier layer through at least one via formed through the barrier layer and through the lower dielectric layer in the first region.

Claim 15

The semiconductor device as in claim 12 , further comprising a conductive layer formed over the substrate surface within the first region, and beneath the lower dielectric layer, wherein at least one via extends down to a top surface of the conductive layer, thereby coupling the bond pad metal to the conductive layer.

Claim 16

The semiconductor device as in claim 13 , wherein the conductive layer comprises a first metal.

Claim 17

The semiconductor device as in claim 13 , wherein the conductive layer is patterned.

Claim 18

The semiconductor device as in claim 15 , wherein the patterned conductive layer is electrically coupled to at least one of the active devices.

Claim 19

The semiconductor device as in claim 14 , wherein the first metal and the bond pad metal each comprise one of W, Cu, Al, a copper alloy and an aluminum alloy.

Claim 20

The semiconductor device as in claim 12 , wherein the bond pad metal comprises a composite film including a metal film and a further barrier layer formed at least partially over the metal film.

Claim 21

The semiconductor device as in claim 12 , wherein the bond pad includes an upper surface being coplanar with a top surface of the upper dielectric layer.

Claim 22

The semiconductor device as in claim 12 , wherein the barrier layer is a composite film formed of a plurality of barrier layer films.

Claim 23

The semiconductor device as in claim 12 , wherein the barrier layer is formed of a material selected from the group consisting of Ta, Ti, TaN, TiN, TaSi, TiSi, WSi, and WSiN.

Claim 24

The semiconductor device as in claim 12 , further comprising a conductive wire coupled to an upper surface of the bond pad.

Claim 25

An integrated circuit comprising: a) a substrate having a substrate surface; b) active devices formed on the substrate surface including within a plurality of first regions; c) a patterned conductive layer formed over the substrate surface including within each of the first regions; d) a lower dielectric layer formed over the substrate surface and the patterned conductive layer; e) an upper dielectric layer formed over the lower dielectric layer; f) a barrier layer formed between the upper dielectric layer and the lower dielectric layer at least within each of the first regions; g) a plurality of bond pads, each bond pad formed within an opening formed in the upper dielectric film within a first region and extending down to the corresponding barrier layer, each bond pad comprising a bond pad metal formed in the opening and contacting the barrier layer and coupled to the patterned conductive layer through a plurality of vias formed through the barrier layer and through the lower dielectric layer in the corresponding first region.

Claim 26

An integrated circuit comprising: a) a substrate having a substrate surface; b) active devices formed on the substrate surface including within a plurality of first regions; c) a patterned conductive layer formed over the substrate surface including within each of the first regions; d) a lower dielectric layer formed over the substrate surface and the patterned conductive layer; e) an upper dielectric layer formed over the lower dielectric layer; f) a barrier layer formed between the upper dielectric layer and the lower dielectric layer at least within each of the first regions; g) a plurality of bond pads, each bond pad formed within an opening formed in the upper dielectric film within a first region and extending down to the corresponding barrier layer, each bond pad comprising a bond pad metal formed in the opening and contacting the barrier layer and coupled to the patterned conductive layer through a plurality of vias formed through the barrier layer and through the lower dielectric layer in the corresponding first region.