US6033984A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual damascene with bond pads
Assignee: Polaris Innovations Ltd
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Filing: 1997-12-23
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Granted: 2000-03-07
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Expires: 2017-12-23
Abstract
Abstract An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).
Inventors
- 👤 Rainer Florian Schnabel
- 👤 Xian J. Ning
- 👤 Bruno Spuler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 03:59
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/082; H10W20/084; H10W20/088; H10W72/00; H10W72/01; H10W72/012; H10W72/019; H10W72/20; H10W72/50; H10W72/90; H10W72/071; H10W72/075; H10W72/07551; H10W72/07553; H10W72/251; H10W72/29; H10W72/531; H10W72/536; H10W72/551; H10W72/552; H10W72/5524; H10W72/5525; H10W72/59; H10W72/921; H10W72/931; H10W72/934
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
146 words
A method of forming an integrated circuit, said method comprising: providing an insulating layer, the insulating layer overlying a conductive element; forming an opening in the insulating layer by removing a portion of the insulating layer to expose the conductive element; forming a layer of conductive material over an upper surface of said insulating layer, said layer of conductive material substantially simultaneously filling said opening in the insulating layer; forming a layer of polishing resistant material on said layer of conductive material above said conductive element; and removing portions of said layer of conductive material sufficient to expose said upper surface of said insulating layer wherein a portion of said layer of conductive material beneath said layer of polishing resistant material is removed at a slower rate than a portion of said layer of conductive material that is not beneath said layer of polishing resistant material.
Claim 2
Independent Claim
146 words
A method of forming an integrated circuit, said method comprising: providing an insulating layer, the insulating layer overlying a conductive element; forming an opening in the insulating layer by removing a portion of the insulating layer to expose the conductive element; forming a layer of conductive material over an upper surface of said insulating layer, said layer of conductive material substantially simultaneously filling said opening in the insulating layer; forming a layer of polishing resistant material on said layer of conductive material above said conductive element; and removing portions of said layer of conductive material sufficient to expose said upper surface of said insulating layer wherein a portion of said layer of conductive material beneath said layer of polishing resistant material is removed at a slower rate than a portion of said layer of conductive material that is not beneath said layer of polishing resistant material.
Claim 3
Dependent Claim
33 words
The method of claim 1 wherein removing a portion of the insulating layer comprises etching a portion of the insulating material using an etchant source gas that comprises C 4 F 8 .
Claim 4
Dependent Claim
18 words
The method of claim 1 wherein said etchant source gas further includes a quantity of O 2 .
Claim 5
Dependent Claim
63 words
The method of claim 1 wherein forming an opening in the insulating layer comprises first and second etching steps, the first etching step removing a first thickness of the insulating layer and the second etching step removing a second thickness of the insulating layer, the insulating layer having a total thickness equal to the sum of the first thickness and the second thickness.
Claim 6
Dependent Claim
19 words
The method of claim 4 wherein the second etching step forms a larger opening than the second etching step.
Claim 7
Dependent Claim
28 words
The method of claim 4 wherein at least one of said first and second etching steps uses an etchant source gas that comprises C 4 F 8 .
Claim 8
Dependent Claim
17 words
The method of claim 6 wherein said etchant source gas includes a quantity of O 2 .
Claim 9
Dependent Claim
19 words
The method of claim 1 wherein the polishing resistant material comprises at least one of Ti, SiON, and SiN.
Claim 10
Dependent Claim
19 words
The method of claim 1 wherein removing portions of said layer of conductive material comprises forming a bond pad.
Claim 11
Dependent Claim
16 words
The method of claim 9 and further comprising connecting a bond wire to the bond pad.
Claim 12
Independent Claim
180 words
A method of fabricating an integrated circuit, the method comprising: providing a semiconductor device that includes an insulating layer disposed over a conductive element, forming a first opening in the insulating layer by removing a portion of the insulating layer above the conductive element such that the conductive element remains covered by a thinner portion of the insulating layer, anisotropically etching a portion of the insulating layer surrounding the first opening thereby removing the thinner portion of the insulating layer and exposing the conductive element, forming a conductive layer over an upper surface of the insulating layer, the conductive layer contacting the conductive element, forming a region of polishing resistant material over the conductive layer above the first opening prior to removing the conductive layer from within the first opening and removing the conductive layer from the upper surface of the insulating material wherein a portion of the conductive layer beneath the layer of polishing resistant material is removed at a slower rate than a portion of the conductive layer that is not beneath the layer of polishing resistant material.
Claim 13
Independent Claim
180 words
A method of fabricating an integrated circuit, the method comprising: providing a semiconductor device that includes an insulating layer disposed over a conductive element, forming a first opening in the insulating layer by removing a portion of the insulating layer above the conductive element such that the conductive element remains covered by a thinner portion of the insulating layer, anisotropically etching a portion of the insulating layer surrounding the first opening thereby removing the thinner portion of the insulating layer and exposing the conductive element, forming a conductive layer over an upper surface of the insulating layer, the conductive layer contacting the conductive element, forming a region of polishing resistant material over the conductive layer above the first opening prior to removing the conductive layer from within the first opening and removing the conductive layer from the upper surface of the insulating material wherein a portion of the conductive layer beneath the layer of polishing resistant material is removed at a slower rate than a portion of the conductive layer that is not beneath the layer of polishing resistant material.
Claim 14
Dependent Claim
22 words
The method of claim 11 wherein the insulating layer comprises one of an oxide layer, a glass layer or a polyimide layer.
Claim 15
Dependent Claim
46 words
The method of claim 11 wherein the first opening has a first lateral dimension "d" and the portion of the insulating layer surrounding the first opening has a second lateral dimension "t", and wherein the ratio of "d" to "t" is between about 0.5 and 0.9.
Claim 16
Dependent Claim
40 words
The method of claim 11 wherein the conductive element serves as an etch stop such that the anisotropically etching a portion of the insulating layer is stopped once a predetermined amount of conductive element material is evident in the etchant.
Claim 17
Dependent Claim
15 words
The method of claim 11 wherein forming a conductive layer comprises forming a metal layer.
Claim 18
Dependent Claim
31 words
The method of claim 11 wherein removing the conductive layer from the upper surface of the insulating material further comprises removing portions of the conductive layer from within the first opening.
Claim 19
Independent Claim
126 words
A method of forming a via hole though an insulator, the method comprising: etching a via hole in the insulator, said etching using C 4 F 8 and O 2 ; forming a bond pad trench around the via hole; placing a layer of conductive material over the insulator; placing a layer of polishing resistant material on the layer of conductive material; forming a bond pad by removing a portion of the layer of conductive material sufficient to expose an upper surface of the insulator wherein a portion of the layer of conductive material beneath the layer of polishing resistant material is removed at a slower rate than a portion of the layer of conductive material that is not beneath the layer of polishing resistant material.
Claim 20
Independent Claim
126 words
A method of forming a via hole though an insulator, the method comprising: etching a via hole in the insulator, said etching using C 4 F 8 and O 2 ; forming a bond pad trench around the via hole; placing a layer of conductive material over the insulator; placing a layer of polishing resistant material on the layer of conductive material; forming a bond pad by removing a portion of the layer of conductive material sufficient to expose an upper surface of the insulator wherein a portion of the layer of conductive material beneath the layer of polishing resistant material is removed at a slower rate than a portion of the layer of conductive material that is not beneath the layer of polishing resistant material.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-03-07 | 2003-09-06 | 2004-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-03-07 | 2007-09-06 | 2008-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-03-07 | 2011-09-06 | 2012-03-07 | $7700.00 | Window Closed / Lapsed |