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US6803285B2
Expired / Lapsed
US
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Method of fabricating dual threshold voltage n-channel and p-channel mosfets with a single extra masked implant operation
Assignee: Intel Corp
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Filing: 2002-12-04
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Granted: 2004-10-12
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Expires: 2022-12-04
Abstract
Abstract A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.
Inventors
- 👤 Kaizad R. Mistry
- 👤 Ian R. Post
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 20:20
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
209 words
A method of forming a semiconductor device, comprising: forming a plurality of isolation structures in the substrate, the isolation structures defining at least a low Vt NFET region, a high Vt NFET region, a high Vt PFET region, and a low Vt PFET region; patterning a first masking layer to expose at least the low Vt NFET region and the high Vt NFET region and to cover at least the high Vt PFET region and the low Vt PFET region; performing a p-well implant and a low Vtn implant into the exposed NFET regions; removing the first masking layer; patterning a second masking layer to expose at least the high Vt PFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt NFET region; performing an n-well implant and a high Vtp implant into the exposed PFET regions; removing the second masking layer; patterning a third masking layer to expose at least the high Vt NFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt PFET region; and performing a high Vtn implant into at least the exposed high Vt NFET and low Vt PFET regions.
Claim 2
Independent Claim
209 words
A method of forming a semiconductor device, comprising: forming a plurality of isolation structures in the substrate, the isolation structures defining at least a low Vt NFET region, a high Vt NFET region, a high Vt PFET region, and a low Vt PFET region; patterning a first masking layer to expose at least the low Vt NFET region and the high Vt NFET region and to cover at least the high Vt PFET region and the low Vt PFET region; performing a p-well implant and a low Vtn implant into the exposed NFET regions; removing the first masking layer; patterning a second masking layer to expose at least the high Vt PFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt NFET region; performing an n-well implant and a high Vtp implant into the exposed PFET regions; removing the second masking layer; patterning a third masking layer to expose at least the high Vt NFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt PFET region; and performing a high Vtn implant into at least the exposed high Vt NFET and low Vt PFET regions.
Claim 3
Dependent Claim
24 words
The method of claim 1 , wherein the low Vtn implant comprises implanting a p-type dopant at a first dose and a first energy.
Claim 4
Dependent Claim
16 words
The method of claim 1 , wherein the high Vtp implant comprises implanting an n-type dopant.
Claim 5
Dependent Claim
42 words
The method of claim 1 , wherein the low Vtn implant comprises implanting a p-type dopant at a first dose and a first energy, and the high Vtn implant comprises implanting a p-type dopant at a second dose and a second energy.
Claim 6
Independent Claim
150 words
A method of forming transistors, comprising: forming a first p-well, and a second p-well; implanting a p-type dopant, at a first dose and energy, into the first and second p-wells; forming a first n-well, and a second n-well; implanting an n-type dopant, at a second dose and energy, into the first and second n-wells; implanting a p-type dopant, at a third dose and energy, into the second p-well and the second n-well; and forming a first NPET having a first threshold voltage in the first p-well, a second NFET having a second threshold voltage in the second p-well, a first PFET having a third threshold voltage, in the first n-well, and a second PFET having a fourth threshold in the second n-well; wherein the second threshold voltage is greater in magnitude than the first threshold voltage, and the third threshold voltage is greater in magnitude than the fourth threshold voltage.
Claim 7
Independent Claim
150 words
A method of forming transistors, comprising: forming a first p-well, and a second p-well; implanting a p-type dopant, at a first dose and energy, into the first and second p-wells; forming a first n-well, and a second n-well; implanting an n-type dopant, at a second dose and energy, into the first and second n-wells; implanting a p-type dopant, at a third dose and energy, into the second p-well and the second n-well; and forming a first NPET having a first threshold voltage in the first p-well, a second NFET having a second threshold voltage in the second p-well, a first PFET having a third threshold voltage, in the first n-well, and a second PFET having a fourth threshold in the second n-well; wherein the second threshold voltage is greater in magnitude than the first threshold voltage, and the third threshold voltage is greater in magnitude than the fourth threshold voltage.
Claim 8
Dependent Claim
40 words
The method of claim 5 , further comprising patterning a masking layer such that the first p-well and the first n-well are protected from ion implantation, and the second p-well and the second n-well are not protected from ion implantation.
Claim 9
Dependent Claim
12 words
The method of claim 6 , further comprising removing the masking layer.
Claim 10
Dependent Claim
21 words
The method of claim 5 , wherein the n-type dopant is selected from the group consisting of phosphorus, antimony and arsenic.
Claim 11
Dependent Claim
20 words
The method of claim 5 , wherein the p-type dopant selected from the group consisting of boron, BF2, and indium.
Claim 12
Dependent Claim
198 words
A manufacturing process, comprising: forming at least a low Vt NFET region, a high Vt NFET region, a high Vt PFET region, and a low Vt PFET region in a substrate; patterning a first mask layer to expose at least the low Vt NFET region and the high Vt NFET region and to cover at least the high Vt PFET region and the low Vt PFET region; performing a p-well implant and a high Vtn implant into the exposed NFET regions; removing the first mask layer, patterning a second mask layer to expose at least the high Vt PFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt NFET region; performing an n-well implant and a low Vtp implant into the exposed PFET regions; removing the second mask layer; patterning a third mask layer to expose at least the low Vt NFET region and the high Vt PFET region and to cover at least the high Vt NFET region and the low Vt PFET region; and performing a high Vtp implant into at least the exposed low Vt NFET region and the high Vt PFET region.
Claim 13
Dependent Claim
198 words
A manufacturing process, comprising: forming at least a low Vt NFET region, a high Vt NFET region, a high Vt PFET region, and a low Vt PFET region in a substrate; patterning a first mask layer to expose at least the low Vt NFET region and the high Vt NFET region and to cover at least the high Vt PFET region and the low Vt PFET region; performing a p-well implant and a high Vtn implant into the exposed NFET regions; removing the first mask layer, patterning a second mask layer to expose at least the high Vt PFET region and the low Vt PFET region and to cover at least the low Vt NFET region and the high Vt NFET region; performing an n-well implant and a low Vtp implant into the exposed PFET regions; removing the second mask layer; patterning a third mask layer to expose at least the low Vt NFET region and the high Vt PFET region and to cover at least the high Vt NFET region and the low Vt PFET region; and performing a high Vtp implant into at least the exposed low Vt NFET region and the high Vt PFET region.
Claim 14
Dependent Claim
38 words
The method of claim 10 , wherein performing a p-well implant and a high Vtn implant comprises implanting a p-type dopant at a first dose and energy and implanting a p-type dopant at a second dose and energy.
Claim 15
Dependent Claim
38 words
The method of claim 10 , wherein performing an n-well implant and a low Vtp implant comprises implanting an n-type dopant at a first dose and energy and implanting an n-type dopant at a second dose and energy.
Claim 16
Independent Claim
150 words
A method of forming transistors, comprising: forming a first p-well, and a second p-well; implanting a p-type dopant, at a first dose and energy, into the first and second p-wells; forming a first n-well, and a second n-well; implanting an n-type dopant, at a second dose and energy, into the first and second n-wells; implanting an n-type dopant, at a third dose and energy, into the first p-well and the first n-well; and forming a first NFET having a first threshold voltage in the first p-well, a second NFET having a second threshold voltage in the second p-well, a first PFET having a third threshold voltage, in the first n-well, and a second PFET having a fourth threshold in the second n-well; wherein the second threshold voltage is greater in magnitude than the first threshold voltage, and the third threshold voltage is greater in magnitude than the fourth threshold voltage.
Claim 17
Independent Claim
150 words
A method of forming transistors, comprising: forming a first p-well, and a second p-well; implanting a p-type dopant, at a first dose and energy, into the first and second p-wells; forming a first n-well, and a second n-well; implanting an n-type dopant, at a second dose and energy, into the first and second n-wells; implanting an n-type dopant, at a third dose and energy, into the first p-well and the first n-well; and forming a first NFET having a first threshold voltage in the first p-well, a second NFET having a second threshold voltage in the second p-well, a first PFET having a third threshold voltage, in the first n-well, and a second PFET having a fourth threshold in the second n-well; wherein the second threshold voltage is greater in magnitude than the first threshold voltage, and the third threshold voltage is greater in magnitude than the fourth threshold voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-10-12 | 2008-04-12 | 2008-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-10-12 | 2012-04-12 | 2012-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-10-12 | 2016-04-12 | 2016-10-12 | $7700.00 | Window Closed / Lapsed |