Patent DE475200C successfully refreshed from Google Patents.
Patent US6780694B2 successfully refreshed from Google Patents.
US6780694B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS transistor
Assignee: GlobalFoundries US Inc
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Filing: 2003-01-08
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Granted: 2004-08-24
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Expires: 2023-01-08
Abstract
Abstract A method of fabricating a semiconductor transistor device comprises the steps as follows. Provide a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top. Form a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed. Form an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode. Remove the planarizing layer. Form source/drain extensions in the substrate protected from the short channel effect. Form sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode. Form source/drain regions in the substrate. Form silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
Inventors
- 👤 Bruce B. Doris
- 👤 Omer H. Dokumaci
- 👤 Jack A. Mandelman
- 👤 Carl J. Radens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:35
CPC Classifications
H; H10; H10P; H10P10/00; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0179; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10P30/00; H10P30/20; H10P30/222
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
161 words
A method of forming a semiconductor transistor device, comprising the steps of: providing a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top; forming a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed; forming an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode; removing the planarizing layer; forming source/drain extensions in the substrate protected from the short channel effect; forming sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode; forming source/drain regions in the substrate; and forming silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
Claim 2
Independent Claim
161 words
A method of forming a semiconductor transistor device, comprising the steps of: providing a semiconductor substrate with a gate dielectric layer thereover and a lower gate electrode structure formed over the gate dielectric layer with the lower gate electrode structure having a lower gate top; forming a planarizing layer over the gate dielectric layer leaving the gate top of the lower gate electrode structure exposed; forming an upper gate structure over the lower gate electrode structure to form a T-shaped gate electrode with an exposed lower surface of the upper gate surface and exposed vertical sidewalls of the gate electrode; removing the planarizing layer; forming source/drain extensions in the substrate protected from the short channel effect; forming sidewall spacers adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewalls of the T-shaped gate electrode; forming source/drain regions in the substrate; and forming silicide layers on top of the T-shaped gate electrode and above the source/drain regions.
Claim 3
Dependent Claim
82 words
The method of claim 1 including the steps of: recessing the lower gate structure to form a recessed lower gate within the planarizing layer before forming the upper gate; etching the planarizing layer to define a wide recess therein having a width greater than the width of the lower gate electrode structure; and then forming the upper gate within the wide recess on the recessed lower gate whereby the lower gate electrode structure and upper gate structure form the T-shaped gate electrode.
Claim 4
Dependent Claim
35 words
The method of claim 2 including the step of forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode.
Claim 5
Dependent Claim
46 words
The method of claim 2 including the steps of: forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 6
Dependent Claim
47 words
The method of claim 2 including the steps of: forming NFET extensions by a combination of a vertical angle ion implant of arsenic ions and a tilted angle ion implant of arsenic ions, and forming PFET extensions by only a vertical angle ion implant of boron ions.
Claim 7
Dependent Claim
72 words
The method of claim 2 including the steps of: forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 8
Dependent Claim
98 words
The method of claim 2 including the steps of: forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 9
Dependent Claim
68 words
The method of claim 1 including the steps of: recessing the lower gate structure to form a recessed lower gate within the planarizing layer before forming the upper gate; then growing the upper gate on the surface of the lower gate within the recess and overgrowing the upper gate above the planarizing layer whereby the lower gate electrode structure and upper gate structure form the T-shaped gate electrode.
Claim 10
Dependent Claim
35 words
The method of claim 8 including the step of forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode.
Claim 11
Dependent Claim
46 words
The method of claim 8 including the steps of: forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 12
Dependent Claim
47 words
The method of claim 8 including the steps of: forming NFET extensions by a combination of a vertical angle ion implant of arsenic ions and a tilted angle ion implant of arsenic ions, and forming PFET extensions by only a vertical angle ion implant of boron ions.
Claim 13
Dependent Claim
72 words
The method of claim 8 including the steps of: forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 14
Dependent Claim
98 words
The method of claim 8 including the steps of: forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 15
Dependent Claim
47 words
The method of claim 1 including the steps of: partially recessing the planarizing layer below the level of the lower gate top before forming the upper gate; then selectively growing the upper gate on exposed surfaces of the lower gate top to form the T-shaped gate electrode.
Claim 16
Dependent Claim
35 words
The method of claim 14 including the step of forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode.
Claim 17
Dependent Claim
46 words
The method of claim 14 including the steps of: forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 18
Dependent Claim
47 words
The method of claim 14 including the steps of: forming NFET extensions by a combination of a vertical angle ion implant of arsenic ions and a tilted angle ion implant of arsenic ions, and forming PFET extensions by only a vertical angle ion implant of boron ions.
Claim 19
Dependent Claim
47 words
The method of claim 14 including the steps of: forming NFET extensions by a combination of a vertical angle ion implant of arsenic ions and a tilted angle ion implant of arsenic ions, and forming PFET extensions by only a vertical angle ion implant of boron ions.
Claim 20
Dependent Claim
72 words
The method of claim 14 including the steps of: forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
Claim 21
Dependent Claim
98 words
The method of claim 14 including the steps of: forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming the sidewall spacers of silicon nitride on the exposed lower surface of the upper gate and on the vertical sidewalls of the T-shaped gate electrode, forming NFET extensions by a combination of a vertical angle ion implant of dopant ions and a tilted angle ion implant of dopant ions, and forming PFET extensions by a vertical angle ion implant of dopant ions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-08-24 | 2008-02-23 | 2008-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-08-24 | 2012-02-23 | 2012-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-08-24 | 2016-02-23 | 2016-08-24 | $7700.00 | Window Closed / Lapsed |