US6613623B1 Expired / Lapsed US ⏱️ 0.0 years remaining

High fMAX deep submicron MOSFET

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd

•

Filing: 2001-08-20

•

Granted: 2003-09-02

•

Expires: 2021-08-20

📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method of forming a high fMAX deep submicron MOSFET, comprising the following steps of. A substrate having a MOSFET formed thereon is provided. The MOSFET having a source and a drain and including a silicide portion over a gate electrode. A first ILD layer is formed over the substrate and the MOSFET. The first ILD layer is planarized to expose the silicide portion over the gate electrode. A metal gate portion is formed over the planarized first ILD layer and over the silicide portion over the gate electrode. The metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode. A second ILD layer is formed over the metal gate portion and the first ILD layer. A first metal contact is formed through the second ILD layer contacting the metal gate portion, and a second metal contact is formed through the second and first ILD layers contacting the drain completing the formation of the high fMAX deep submicron MOSFET. Whereby the width of the metal gate portion reduces Rg and increases the fMAX of the high fMAX deep submicron MOSFET.

Inventors

👤 Chao-Chieh Tsai
👤 Shyh-Chyi Wong
👤 Chung-Long Chang

Bibliographic Details

Application Number —

Jurisdiction US

Data Source google_patents

Last Synchronized 2026-10-30 17:11

CPC Classifications

H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D64/519; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10W20/071; H10W20/092; H10D30/00; H10D30/01; H10D30/021; H10D30/0212

Claims Analysis

Total Claims: 48

Claim 1

Independent Claim 186 words

A method of forming a high f MAX deep submicron MOSFET, comprising the sequential steps of: providing a substrate having a MOSFET formed thereon; the MOSFET having a source and a drain and including a silicide portion over a gate electrode; forming a first ILD layer over the substrate and the MOSFET; planarizing the first ILD layer to expose the silicide portion over the gate electrode; forming a metal gate portion over the planarized first ILD layer and over the silicide portion over the gate electrode; the metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode; forming a second ILD layer over the metal gate portion and the first ILD layer; forming a first metal contact through the second ILD layer contacting the metal gate portion and a second metal contact through the second and first ILD layers contacting the drain completing the formation of the high f MAX deep submicron MOSFET; whereby the width of the metal gate portion reduces R g and increases the f MAX of the high f MAX deep submicron MOSFET.

Claim 2

Independent Claim 186 words

Claim 3

Dependent Claim 61 words

The method of claim 1 , including the step of forming a dielectric layer over the substrate and MOSFET before formation of the first ILD layer, and wherein the dielectric layer is removed over the silicide portion over the gate electrode before formation of the metal gate portion; and wherein the first ILD layer is planarized by a chemical-mechanical polishing process.

Claim 4

Dependent Claim 69 words

The method of claim 1 , including the step of forming a dielectric layer comprised of Si 3 N 4 or SiON over the substrate and MOSFET before formation of the first ILD layer, and wherein the dielectric layer is removed over the silicide portion over the gate electrode before formation of the metal gate portion; and wherein the first ILD layer is planarized by a chemical-mechanical polishing process.

Claim 5

Dependent Claim 125 words

The method of claim 1 , wherein the gate electrode is comprised polysilicon; the silicide portion over the gate electrode is comprised of a material selected from the group consisting of CoSi x , CoSi 2 , and TiSi 2 ; the first ILD layer is comprised of a material selected from the group consisting of oxide, silicon oxide, USG and TEOS; the metal gate portion is comprised of a material selected from the group consisting of W, Al, Cu, TiN and Au; the second ILD layer is comprised of a material selected from the group consisting of oxide, silicon oxide, HDP and FSG; and the first and second metal contacts each comprised of a material selected from the group consisting of W and Cu.

Claim 6

Dependent Claim 63 words

The method of claim 1 , wherein the gate electrode is comprised of polysilicon; the silicide portion over the gate electrode is comprised CoSi x ; the first ILD layer is comprised of silicon oxide; the metal gate portion is comprised of tungsten; the second ILD layer is comprised silicon oxide; and the first and second metal contacts each being comprised of tungsten.

Claim 7

Dependent Claim 35 words

The method of claim 1 , wherein the gate electrode has a width of from about 500 to 5000 Å and the metal gate portion has a width of from about 500 to 8000 Å.

Claim 8

Dependent Claim 35 words

The method of claim 1 , wherein the gate electrode has a width of from about 1000 to 3500 Å and the metal gate portion has a width of from about 1000 to 3000 Å.

Claim 9

Dependent Claim 32 words

The method of claim 1 , wherein the gate electrode has a width of about 0.13 μm and the metal gate portion has a width of from about 1800 to 2400 Å.

Claim 10

Dependent Claim 67 words

The method of claim 1 , wherein the gate electrode has a height of from about 1000 to 3000 Å; the silicide portion over the gate electrode has a thickness of from about 270 to 330 Å; the planarized first ILD layer has a thickness of from about 1700 to 1900 Å; and the metal gate portion has a thickness of from about 1800 to 2200 Å.

Claim 11

Dependent Claim 64 words

The method of claim 1 , wherein the gate electrode has a height of from about 1500 to 2200 Å; the silicide portion over the gate electrode has a thickness of from about 290 to 310 Å; the planarized first ILD layer has a thickness of about 1800 Å; and the metal gate portion has a thickness of from about 1900 to 2100 Å.

Claim 12

Dependent Claim 58 words

The method of claim 1 , wherein the gate electrode has a height of from about 1500 to 2200 Å; the silicide portion over the gate electrode has a thickness of about 300 Å; the planarized first ILD layer has a thickness of about 1800 Å; and the metal gate portion has a thickness of about 2000 Å.

Claim 13

Dependent Claim 46 words

The method of claim 1 , wherein the MOSFET includes a source silicide portion over at least a portion of the source and a drain silicide portion over at least a portion of the drain; and wherein the second metal contact contacts the drain silicide portion.

Claim 14

Dependent Claim 52 words

The method of claim 1 , wherein the MOSFET includes a source CoSi x silicide portion over at least a portion of the source and a drain CoSi x silicide portion over at least a portion of the drain; and wherein the second metal contact contacts the drain CoSi x silicide portion.

Claim 15

Dependent Claim 18 words

The method of claim 1 , wherein the first ILD layer is planarized by a chemical-mechanical polishing process.

Claim 16

Dependent Claim 20 words

The method of claim 1 , wherein the high f MAX deep submicron MOSFET is used in an RF circuit.

Claim 17

Dependent Claim 45 words

The method of claim 1 , wherein the gate electrode has a gate oxide thereunder; the gate oxide having a thickness proximate the source and drain to significantly reduce the parasitic capacitance and increase the f MAX of the high f MAX deep submicron MOSFET.

Claim 18

Independent Claim 194 words

A method of forming a high f MAX deep submicron MOSFET, comprising the sequential steps of: providing a substrate having a MOSFET formed thereon; the MOSFET having a source and a drain and including a silicide portion over a gate electrode; the gate electrode having a width of from about 500 to 5000 Å; forming a first ILD layer over the substrate and the MOSFET; chemical-mechanically polishing the first ILD layer to expose the silicide portion over the gate electrode; forming a metal gate portion over the planarized first ILD layer and over the silicide portion over the gate electrode; the metal gate portion having a width of from about 500 to 8000 Å; forming a second ILD layer over the metal gate portion and the first ILD layer; forming a first metal contact through the second ILD layer contacting the metal gate portion and a second metal contact through the second and first ILD layers contacting the drain completing the formation of the high f MAX deep submicron MOSFET; whereby the width of the metal gate portion reduces R g and increases the f MAX of the high f MAX deep submicron MOSFET.

Claim 19

Independent Claim 194 words

A method of forming a high f MAX deep submicron MOSFET, comprising the sequential steps of: providing a substrate having a MOSFET formed thereon; the MOSFET having a source and a drain and including a silicide portion over a gate electrode; the gate electrode having a width of from about 500 to 5000 Å; forming a first ILD layer over the substrate and the MOSFET; chemical-mechanically polishing the first ILD layer to expose the silicide portion over the gate electrode; forming a metal gate portion over the planarized first ILD layer and over the silicide portion over the gate electrode; the metal gate portion having a width of from about 500 to 8000 Å; forming a second ILD layer over the metal gate portion and the first ILD layer; forming a first metal contact through the second ILD layer contacting the metal gate portion and a second metal contact through the second and first ILD layers contacting the drain completing the formation of the high f MAX deep submicron MOSFET; whereby the width of the metal gate portion reduces R g and increases the f MAX of the high f MAX deep submicron MOSFET.

Claim 20

Dependent Claim 48 words

The method of claim 17 , including the step of forming a dielectric layer over the substrate and MOSFET before formation of the first ILD layer, and wherein the dielectric layer is removed over the silicide portion over the gate electrode before formation of the metal gate portion.

Claim 21

Dependent Claim 56 words

The method of claim 17 , including the step of forming a dielectric layer comprised of Si 3 N 4 or SiON over the substrate and MOSFET before formation of the first ILD layer, and wherein the dielectric layer is removed over the silicide portion over the gate electrode before formation of the metal gate portion.

Claim 22

Dependent Claim 125 words

The method of claim 17 , wherein the gate electrode is comprised of polysilicon; the silicide portion over the gate electrode is comprised of a material selected from the group consisting of CoSi x , CoSi 2 and TiSi 2 ; the first ILD layer is comprised of a material selected from the group consisting of oxide, silicon oxide, USG and TEOS; the metal gate portion is comprised of a material selected from the group consisting of W, Al, Cu, TiN and Au; the second ILD layer is comprised of a material selected from the group consisting of oxide, silicon oxide, HDP and FSG; and the first and second metal contacts each comprised of a material selected from the group consisting of W and Cu.

Claim 23

Dependent Claim 63 words

The method of claim 17 , wherein the gate electrode is comprised of polysilicon; the silicide portion over the gate electrode is comprised CoSi x ; the first ILD layer is comprised of silicon oxide; the metal gate portion is comprised of tungsten; the second ILD layer is comprised silicon oxide; and the first and second metal contacts each being comprised of tungsten.

Claim 24

Dependent Claim 35 words

The method of claim 17 , wherein the gate electrode has a width of from about 1000 to 3500 Å and the metal gate portion has a width of from about 1000 to 3000 Å.

Claim 25

Dependent Claim 32 words

The method of claim 17 , wherein the gate electrode has a width of about 0.13 μm and the metal gate portion has a width of from about 1800 to 2400 Å.

Claim 26

Dependent Claim 67 words

The method of claim 17 , wherein the gate electrode has a height of from about 1000 to 3000 Å; the silicide portion over the gate electrode has a thickness of from about 270 to 330 Å; the planarized first ILD layer has a thickness of from about 1700 to 1900 Å; and the metal gate portion has a thickness of from about 1800 to 2200 Å.

Claim 27

Dependent Claim 64 words

The method of claim 17 , wherein the gate electrode has a height of from about 1500 to 2200 Å; the silicide portion over the gate electrode has a thickness of from about 290 to 310 Å; the planarized first ILD layer has a thickness of about 1800 Å; and the metal gate portion has a thickness of from about 1900 to 2100 Å.

Claim 28

Dependent Claim 60 words

The method of claim 17 , wherein the gate electrode has a height of from about 1500 to 2200 Å; the silicide portion 30 over the gate electrode 18 has a thickness of about 300 Å; the planarized first ILD layer has a thickness of about 1800 Å; and the metal gate portion has a thickness of about 2000 Å.

Claim 29

Dependent Claim 46 words

The method of claim 17 , wherein the MOSFET includes a source silicide portion over at least a portion of the source and a drain silicide portion over at least a portion of the drain; and wherein the second metal contact contacts the drain silicide portion.

Claim 30

Dependent Claim 52 words

The method of claim 17 , wherein the MOSFET includes a source CoSi x silicide portion over at least a portion of the source and a drain CoSi x silicide portion over at least a portion of the drain; and wherein the second metal contact contacts the drain CoSi x silicide portion.

Claim 31

Dependent Claim 20 words

The method of claim 17 , wherein the high f MAX deep submicron MOSFET is used in an RF circuit.

Claim 32

Dependent Claim 45 words

The method of claim 17 , wherein the gate electrode has a gate oxide thereunder; the gate oxide having a thickness proximate the source and drain to significantly reduce the parasitic capacitance and increase the f MAX of the high f MAX deep submicron MOSFET.

Claim 33

Independent Claim 224 words

A method of forming a high f MAX deep submicron MOSFET, comprising the sequential steps of: providing a substrate having a MOSFET formed thereon; the MOSFET having a source and a drain and including a silicide portion over a gate electrode; the gate electrode having a gate oxide thereunder; the gate oxide having a thickness proximate the source and drain to significantly reduce the parasitic capacitance and increase the f MAX of the high f MAX deep submicron MOSFET; forming a first ILD layer over the substrate and the MOSFET; planarizing the first ILD layer to expose the silicide portion over the gate electrode; forming a metal gate portion over the planarized first ILD layer and over the silicide portion over the gate electrode; the metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode; forming a second ILD layer over the metal gate portion and the first ILD layer; forming a first metal contact through the second ILD layer contacting the metal gate portion and a second metal contact through the second and first ILD layers contacting the drain completing the formation of the high f MAX deep submicron MOSFET; whereby the width of the metal gate portion reduces R g and increases the f MAX of the high f MAX deep submicron MOSFET.

Claim 34

Independent Claim 224 words

A method of forming a high f MAX deep submicron MOSFET, comprising the sequential steps of: providing a substrate having a MOSFET formed thereon; the MOSFET having a source and a drain and including a silicide portion over a gate electrode; the gate electrode having a gate oxide thereunder; the gate oxide having a thickness proximate the source and drain to significantly reduce the parasitic capacitance and increase the f MAX of the high f MAX deep submicron MOSFET; forming a first ILD layer over the substrate and the MOSFET; planarizing the first ILD layer to expose the silicide portion over the gate electrode; forming a metal gate portion over the planarized first ILD layer and over the silicide portion over the gate electrode; the metal gate portion having a width substantially greater than the width of the silicide portion over the gate electrode; forming a second ILD layer over the metal gate portion and the first ILD layer; forming a first metal contact through the second ILD layer contacting the metal gate portion and a second metal contact through the second and first ILD layers contacting the drain completing the formation of the high f MAX deep submicron MOSFET; whereby the width of the metal gate portion reduces R g and increases the f MAX of the high f MAX deep submicron MOSFET.

Claim 35

Dependent Claim 61 words

The method of claim 31 , including the step of forming a dielectric layer over the substrate and MOSFET before formation of the first ILD layer, and wherein the dielectric layer is removed over the silicide portion over the gate electrode before formation of the metal gate portion; and wherein the first ILD layer is planarized by a chemical-mechanical polishing process.

Claim 36

Dependent Claim 69 words

The method of claim 31 , including the step of forming a dielectric layer comprised of Si 3 N 4 or SiON over the substrate and MOSFET before formation of the first ILD layer, and wherein the dielectric layer is removed over the suicide portion over the gate electrode before formation of the metal gate portion; and wherein the first ILD layer is planarized by a chemical-mechanical polishing process.

Claim 37

Dependent Claim 125 words

The method of claim 31 , wherein the gate electrode is comprised polysilicon; the silicide portion over the gate electrode is comprised of a material selected from the group consisting of CoSi x , CoSi 2 , and TiSi 2 ; the first ILD layer is comprised of a material selected from the group consisting of oxide, silicon oxide, USG and TEOS; the metal gate portion is comprised of a material selected from the group consisting of W, Al, Cu, TiN and Au; the second ILD layer is comprised of a material selected from the group consisting of oxide, silicon oxide, HDP and FSG; and the first and second metal contacts each comprised of a material selected from the group consisting of W and Cu.

Claim 38

Dependent Claim 63 words

The method of claim 31 , wherein the gate electrode is comprised of polysilicon; the silicide portion over the gate electrode is comprised CoSi x ; the first ILD layer is comprised of silicon oxide; the metal gate portion is comprised of tungsten; the second ILD layer is comprised silicon oxide; and the first and second metal contacts each being comprised of tungsten.

Claim 39

Dependent Claim 35 words

The method of claim 31 , wherein the gate electrode has a width of from about 500 to 5000 Å and the metal gate portion has a width of from about 500 to 8000 Å.

Claim 40

Dependent Claim 35 words

The method of claim 31 , wherein the gate electrode has a width of from about 1000 to 3500 Å and the metal gate portion has a width of from about 1000 to 3000 Å.

Claim 41

Dependent Claim 32 words

The method of claim 31 , wherein the gate electrode has a width of about 0.13 μm and the metal gate portion has a width of from about 1800 to 2400 Å.

Claim 42

Dependent Claim 67 words

The method of claim 31 , wherein the gate electrode has a height of from about 1000 to 3000 Å; the silicide portion over the gate electrode has a thickness of from about 270 to 330 Å; the planarized first ILD layer has a thickness of from about 1700 to 1900 Å; and the metal gate portion has a thickness of from about 1800 to 2200 Å.

Claim 43

Dependent Claim 64 words

The method of claim 31 , wherein the gate electrode has a height of from about 1500 to 2200 Å; the silicide portion over the gate electrode has a thickness of from about 290 to 310 Å; the planarized first ILD layer has a thickness of about 1800 Å; and the metal gate portion has a thickness of from about 1900 to 2100 Å.

Claim 44

Dependent Claim 58 words

The method of claim 31 , wherein the gate electrode has a height of from about 1500 to 2200 Å; the silicide portion over the gate electrode has a thickness of about 300 Å; the planarized first ILD layer has a thickness of about 1800 Å; and the metal gate portion has a thickness of about 2000 Å.

Claim 45

Dependent Claim 46 words

The method of claim 31 , wherein the MOSFET includes a source silicide portion over at least a portion of the source and a drain silicide portion over at least a portion of the drain; and wherein the second metal contact contacts the drain silicide portion.

Claim 46

Dependent Claim 52 words

The method of claim 31 , wherein the MOSFET includes a source CoSi x siticide portion over at least a portion of the source and a drain CoSi x silicide portion over at least a portion of the drain; and wherein the second metal contact contacts the drain CoSi x silicide portion.

Claim 47

Dependent Claim 18 words

The method of claim 31 , wherein the first ILD layer is planarized by a chemical-mechanical polishing process.

Claim 48

Dependent Claim 20 words

The method of claim 31 , wherein the high f MAX deep submicron MOSFET is used in an RF circuit.

References Cited (Backward Citations)

US5268330A Cited

JPH06349771A Cited

US5554544A Cited

US5818085A Cited

US5943560A Cited

US5915181A Cited

US5739066A Cited

US6063675A Cited

US5731239A Cited

US6204105B1 Cited

US6242311B1 Cited

US5982001A Cited

US6165880A Cited

US6204103B1 Cited

US6184115B1 Cited

US6297109B1 Cited

US6518636B2 Cited

US6445050B1 Cited

US6521955B1 Cited

US6376351B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2006-09-01	2007-03-03	2007-09-02	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2010-09-01	2011-03-03	2011-09-02	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2014-09-01	2015-03-03	2015-09-02	$7700.00	Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag

Select Category

Notes (Optional)