US5943560A
Expired / Lapsed
US
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Method to fabricate the thin film transistor
Assignee: National Science and Technology Council
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Filing: 1996-04-19
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Granted: 1999-08-24
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Expires: 2016-04-19
Abstract
Abstract Ultrahigh vacuum chemical vapor deposition (UHV/CVD) and chemical mechanical polishing (CMP) systems are used in a method which can fabricate polycrystalline silicon (poly-Si) and polycrystalline silicon-germanium (poly-Si 1-x -Ge x ) thin film transistors at low temperature and low thermal budget. Poly-Si and poly-Si 1-x -Ge x can be deposited by UHV/CVD without any anneal step. And due to the ultra low base pressure and ultraclean growth environment, the As-deposited poly films have low defect densities. However, the surface morphology retards the usage of the fabricating top-gate poly TFT's. In this invention, the CMP system is used for improving the surface morphology, high performance poly-Si and poly-Si 1-x -Ge x TFT's can be obtained.
Inventors
- 👤 Chun-Yen Chang
- 👤 Tan-Fu Lei
- 👤 Hsiao-Yi Lin
- 👤 Juing-Yi Cheng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 02:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2921; H10P14/2922; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01314; H10P52/00; H10P52/40; H10P52/402
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
186 words
A method for fabricating a thin film transistor comprising the steps of: depositing poly-Si or poly-Si 1-x -Ge x on an insulation dielectric layer using a UHV/CVD system to form a channel, polishing and reducing a surface roughness of the channel using a CMP system, forming a gate dielectric layer on the polished channel, depositing a gate of either poly-Si or poly-Si 1-x -Ge x on the gate dielectric layer using the UHV/CVD system, depositing under low temperature a SiO 2 layer to form a spacer of a gate sidewall, anisotropic plasma etching the SiO 2 layer, selectively growing high dopant concentration source and drain regions in a recess formed by the anisotropic plasma etching, depositing an insulation dielectric layer covering the gate dielectric layer and the gate, defining two contact holes through the insulation dielectric layer and the gate dielectric layer, and another contact hole through the insulation dielectric layer, and depositing metal into each of the contact holes to form contacting regions for the gate, source, and drain; wherein the source contacting region is connected to the drain contacting region through the polished channel.
Claim 2
Independent Claim
186 words
A method for fabricating a thin film transistor comprising the steps of: depositing poly-Si or poly-Si 1-x -Ge x on an insulation dielectric layer using a UHV/CVD system to form a channel, polishing and reducing a surface roughness of the channel using a CMP system, forming a gate dielectric layer on the polished channel, depositing a gate of either poly-Si or poly-Si 1-x -Ge x on the gate dielectric layer using the UHV/CVD system, depositing under low temperature a SiO 2 layer to form a spacer of a gate sidewall, anisotropic plasma etching the SiO 2 layer, selectively growing high dopant concentration source and drain regions in a recess formed by the anisotropic plasma etching, depositing an insulation dielectric layer covering the gate dielectric layer and the gate, defining two contact holes through the insulation dielectric layer and the gate dielectric layer, and another contact hole through the insulation dielectric layer, and depositing metal into each of the contact holes to form contacting regions for the gate, source, and drain; wherein the source contacting region is connected to the drain contacting region through the polished channel.
Claim 3
Dependent Claim
13 words
The method according to claim 1, wherein the channel is a multilayer structure.
Claim 4
Dependent Claim
35 words
The method according to claim 1, wherein the material for the gate dielectric layer is selected from a group of SiO 2 , Si 3 N 4 , Al 2 O 3 , and SiNO.
Claim 5
Dependent Claim
26 words
The method according to claim 1, further comprising the step of preparing the dielectric layers using one of the following methods: oxidation, nitrogenation, deposition, or dipping.
Claim 6
Dependent Claim
36 words
The method according to claim 1, further comprising the step of doping the gate, the source, and the drain using one of the following: ion implanting, plasma doping, laser assisted ion doping, or gas source doping.
Claim 7
Dependent Claim
14 words
The method according to claim 1, further comprising the step of in situ doping.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |