Method for forming a deep submicron MOSFET device using a silicidation process

Claim 1

A method of fabricating a MOSFET device, on a semiconductor substrate, with a polysilicon gate structure self aligned to a local threshold voltage adjust region, comprising the steps of: depositing a first insulator layer on said semiconductor substrate; forming a photoresist pattern on said first insulator layer, with a first opening in said photoresist pattern, exposing top surface of said first insulator layer, with said first opening comprised with a width between about 0.20 to 0.50 um; forming a second opening, in said first insulator layer, by removing said first insulator layer from said first opening in said photoresist pattern, with said second having a width between about 0.20 to 0.50 um; thermal oxidation to grow a second insulator layer, to be used as a gate insulator layer, on the surface of said semiconductor substrate, exposed in said second opening; ion implanting a first conductivity imparting dopant, through said second insulator layer, and into an area of said semiconductor substrate, defined by said second opening, to create said local threshold adjust region; depositing a polysilicon layer, completely filling said second opening, and on top surface of said first insulator layer; depositing a first metal layer on said polysilicon layer; annealing to convert all of said polysilicon layer on top surface of said first insulator layer, and to convert a top portion of said polysilicon layer, in said second opening, to a metal silicide layer, while leaving a lower portion of said polysilicon, in said second opening, unreacted; removal of said metal silicide layer, from top surface of said first insulator layer, and removal of said metal silicide layer from top surface of said lower portion of said polysilicon layer, in said opening, resulting in the formation of said polysilicon gate structure, in said second opening, self aligned to underlying, said local threshold voltage adjust region; removal of said first insulator layer; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to from a lightly doped source and drain region; depositing a third insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said third insulator layer, to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a fourth insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said fourth insulator layer, to expose top surface of said heavily doped source and drain region; depositing a second metal layer on top surface of said fourth insulator layer, on top surface of said heavily doped source and drain region; and patterning of said second metal layer, to form a metal contact structure to said heavily doped source and drain region.

Claim 2

A method of fabricating a MOSFET device, on a semiconductor substrate, with a polysilicon gate structure self aligned to a local threshold voltage adjust region, comprising the steps of: depositing a first insulator layer on said semiconductor substrate; forming a photoresist pattern on said first insulator layer, with a first opening in said photoresist pattern, exposing top surface of said first insulator layer, with said first opening comprised with a width between about 0.20 to 0.50 um; forming a second opening, in said first insulator layer, by removing said first insulator layer from said first opening in said photoresist pattern, with said second having a width between about 0.20 to 0.50 um; thermal oxidation to grow a second insulator layer, to be used as a gate insulator layer, on the surface of said semiconductor substrate, exposed in said second opening; ion implanting a first conductivity imparting dopant, through said second insulator layer, and into an area of said semiconductor substrate, defined by said second opening, to create said local threshold adjust region; depositing a polysilicon layer, completely filling said second opening, and on top surface of said first insulator layer; depositing a first metal layer on said polysilicon layer; annealing to convert all of said polysilicon layer on top surface of said first insulator layer, and to convert a top portion of said polysilicon layer, in said second opening, to a metal silicide layer, while leaving a lower portion of said polysilicon, in said second opening, unreacted; removal of said metal silicide layer, from top surface of said first insulator layer, and removal of said metal silicide layer from top surface of said lower portion of said polysilicon layer, in said opening, resulting in the formation of said polysilicon gate structure, in said second opening, self aligned to underlying, said local threshold voltage adjust region; removal of said first insulator layer; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to from a lightly doped source and drain region; depositing a third insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said third insulator layer, to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a fourth insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said fourth insulator layer, to expose top surface of said heavily doped source and drain region; depositing a second metal layer on top surface of said fourth insulator layer, on top surface of said heavily doped source and drain region; and patterning of said second metal layer, to form a metal contact structure to said heavily doped source and drain region.

Claim 13

A method of fabricating a MOSFET device, on a semiconductor substrate, with a polysilicon gate structure, between about 0.20 to 0.50 urn. in width. self aligned to a local threshold voltage adjust region, comprising the steps of: depositing a first insulator layer on said semiconductor substrate; forming a photoresist pattern on said first insulator layer, with a first opening between about 0.20 to 0.50 urn. in width, in said photoresist pattern, exposing top surface of said first insulator layer; forming a second opening, in said first insulator layer, by removing said first insulator layer, from an area defined by said first opening in said photoresist pattern with said second opening having a width between about 0.20 to 0.50 um: thermal oxidation to grow a second insulator layer, to be used as a gate insulator layer, on the surface of said semiconductor substrate, exposed in said second opening; ion implanting a first conductivity imparting dopant through said second insulator layer, and into an area of said semiconductor substrate, defined by said second opening, to create said local threshold voltage adjust region; depositing a polysilicon layer, completely filling said second opening, and on top surface of said first insulator layer; depositing a titanium layer on said polysilicon layer; annealing to convert all of said polysilicon layer on top surface of said first insulator layer, and to convert a top portion of said polysilicon layer, in said second opening, to a titanium silicide layer, while leaving a lower portion of said polysilicon layer, in said second opening, unreacted; removal of said titanium silicide layer from the top surface of said first insulator layer, and removal of said titanium silicide layer the top surface of said lower portion of said polysilicon layer, in said second opening, resulting in formation of said polysilicon gate structure, in said second opening, self aligned to underlying, said local threshold voltage adjust region; removal of said first insulator layer; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to form a lightly doped source and drain region; depositing a third insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said third insulator layer to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a fourth insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said fourth insulator layer, to expose top surface of said heavily doped source and drain region; depositing a metal layer on the top surface of said fourth insulator layer, on the top surface of said heavily doped source and drain region exposed in said contact hole; and patterning of said metal layer to form metal contact structure to said heavily doped source and drain region.

Claim 14

A method of fabricating a MOSFET device, on a semiconductor substrate, with a polysilicon gate structure, between about 0.20 to 0.50 urn. in width. self aligned to a local threshold voltage adjust region, comprising the steps of: depositing a first insulator layer on said semiconductor substrate; forming a photoresist pattern on said first insulator layer, with a first opening between about 0.20 to 0.50 urn. in width, in said photoresist pattern, exposing top surface of said first insulator layer; forming a second opening, in said first insulator layer, by removing said first insulator layer, from an area defined by said first opening in said photoresist pattern with said second opening having a width between about 0.20 to 0.50 um: thermal oxidation to grow a second insulator layer, to be used as a gate insulator layer, on the surface of said semiconductor substrate, exposed in said second opening; ion implanting a first conductivity imparting dopant through said second insulator layer, and into an area of said semiconductor substrate, defined by said second opening, to create said local threshold voltage adjust region; depositing a polysilicon layer, completely filling said second opening, and on top surface of said first insulator layer; depositing a titanium layer on said polysilicon layer; annealing to convert all of said polysilicon layer on top surface of said first insulator layer, and to convert a top portion of said polysilicon layer, in said second opening, to a titanium silicide layer, while leaving a lower portion of said polysilicon layer, in said second opening, unreacted; removal of said titanium silicide layer from the top surface of said first insulator layer, and removal of said titanium silicide layer the top surface of said lower portion of said polysilicon layer, in said second opening, resulting in formation of said polysilicon gate structure, in said second opening, self aligned to underlying, said local threshold voltage adjust region; removal of said first insulator layer; ion implanting a second conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, to form a lightly doped source and drain region; depositing a third insulator layer on said semiconductor substrate, and on said polysilicon gate structure; anisotropic etching of said third insulator layer to form an insulator spacer on the sides of said polysilicon gate structure; ion implanting a third conductivity imparting dopant into an area of said semiconductor substrate, not covered by said polysilicon gate structure, and not covered by said insulator spacer, to form a heavily doped source and drain region; depositing a fourth insulator layer on said semiconductor substrate, and on said polysilicon gate structure; opening a contact hole in said fourth insulator layer, to expose top surface of said heavily doped source and drain region; depositing a metal layer on the top surface of said fourth insulator layer, on the top surface of said heavily doped source and drain region exposed in said contact hole; and patterning of said metal layer to form metal contact structure to said heavily doped source and drain region.