US6440830B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of copper-polysilicon gate formation
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2000-08-30
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Granted: 2002-08-27
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Expires: 2020-08-30
Abstract
Abstract In one embodiment, a method for manufacturing a field effect transistor ( 100 ) includes forming a polysilicon gate ( 104 ) on a surface ( 106 ) of a semiconductor substrate ( 102 ) in association with adjacent source/drain regions ( 110, 112 ) and forming dielectric spacers ( 124, 126 ) on sides of the polysilicon gate. The method further includes forming a trench ( 202 ) between the dielectric spacers on a surface ( 200 ) of the polysilicon gate and filling at least a portion of the trench with barrier and copper or other high conductivity metal to form a copper-polysilicon gate of the field effect transistor.
Inventors
- 👤 Sergey Lopatin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:05
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/01324; H10D64/017; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/664; H10P; H10P14/00; H10P14/40; H10P14/418; H10P14/46
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
157 words
A method of manufacturing a field effect transistor, the method comprising: forming a polysilicon gate on a semiconductor substrate in association with adjacent source/drain regions; forming dielectric spacers on sides of the polysilicon gate; forming a trench between the dielectric spacers on a surface of the polysilicon gate; filling at least a portion of the trench with copper to form a copper-polysilicon gate of the field effect transistor; depositing a dielectric layer over the copper-polysilicon gate, dielectric spacers and source/drain regions associated with the semiconductor substrate; planarizing a top surface portion of the field effect transistor, wherein planarizing comprises removing a portion of the dielectric layer to a predetermined depth related to a thickness of the dielectric spacers; selectively depositing electroless metal on the copper-polysilicon gate; removing selected portions of the dielectric layer to expose the adjacent source/drain regions and the electroless metal on the copper-polysilicon gate; and forming a nickel silicide on the adjacent source/drain regions.
Claim 2
Independent Claim
157 words
A method of manufacturing a field effect transistor, the method comprising: forming a polysilicon gate on a semiconductor substrate in association with adjacent source/drain regions; forming dielectric spacers on sides of the polysilicon gate; forming a trench between the dielectric spacers on a surface of the polysilicon gate; filling at least a portion of the trench with copper to form a copper-polysilicon gate of the field effect transistor; depositing a dielectric layer over the copper-polysilicon gate, dielectric spacers and source/drain regions associated with the semiconductor substrate; planarizing a top surface portion of the field effect transistor, wherein planarizing comprises removing a portion of the dielectric layer to a predetermined depth related to a thickness of the dielectric spacers; selectively depositing electroless metal on the copper-polysilicon gate; removing selected portions of the dielectric layer to expose the adjacent source/drain regions and the electroless metal on the copper-polysilicon gate; and forming a nickel silicide on the adjacent source/drain regions.
Claim 3
Dependent Claim
43 words
The method of claim 1 , wherein filling the trench comprises: depositing a barrier metal on the surface of the polysilicon gate; depositing a copper seed layer on the barrier metal; and electroplating copper to fill at least a portion of the trench.
Claim 4
Dependent Claim
25 words
The method of claim 1 , wherein planarizing comprises removing a portion of the semiconductor substrate to expose a top portion of the dielectric spacers.
Claim 5
Dependent Claim
20 words
The method of claim 1 , further comprising: forming copper interconnections to the copper-polysilicon gate and the adjacent source/drain regions.
Claim 6
Dependent Claim
48 words
The method of claim 4 , wherein forming copper interconnections comprises: depositing a barrier metal on the portion of the copper-polysilicon gate and contact portions of the adjacent source/drain regions; and forming electrical contacts between the barrier metal and a copper conducting layer formed on the semiconductor substrate.
Claim 7
Dependent Claim
56 words
The method of claim 5 , wherein removing selected portions of the dielectric layer comprises: etching a gate contact in the dielectric layer, the etching stopping when the dielectric spacers are exposed by the etching; and etching source/drain contacts in the dielectric layer, the etching stopping when the adjacent source/drain regions are exposed by the etching.
Claim 8
Dependent Claim
30 words
The method of claim 1 , further comprising: selectively depositing electroless material on the copper-polysilicon gate and the adjacent source/drain regions to form electrical contacts for the field effect transistor.
Claim 9
Dependent Claim
39 words
The method of claim 1 , wherein forming a nickel silicide further comprises: depositing a layer of nickel across the semiconductor substrate; annealing to form nickel silicide on the adjacent source/drain regions; and removing nickel from the electroless metal.
Claim 10
Dependent Claim
101 words
A semiconductor manufacturing process comprising the acts of: forming a polysilicon gate on a semiconductor substrate; forming dielectric spacers on opposing sides of the polysilicon gate; etching a predetermined thickness from a surface of the polysilicon gate to define a trench between the dielectric spacers; depositing a barrier metal on the surface of the polysilicon gate; forming a copper gate on the barrier metal; selectively depositing an electroless barrier metal on the copper gate; depositing a film of nickel on the semiconductor substrate including on exposed source/drain regions formed adjacent the polysilicon gate; and forming nickel silicide on the source/drain regions.
Claim 11
Dependent Claim
101 words
A semiconductor manufacturing process comprising the acts of: forming a polysilicon gate on a semiconductor substrate; forming dielectric spacers on opposing sides of the polysilicon gate; etching a predetermined thickness from a surface of the polysilicon gate to define a trench between the dielectric spacers; depositing a barrier metal on the surface of the polysilicon gate; forming a copper gate on the barrier metal; selectively depositing an electroless barrier metal on the copper gate; depositing a film of nickel on the semiconductor substrate including on exposed source/drain regions formed adjacent the polysilicon gate; and forming nickel silicide on the source/drain regions.
Claim 12
Dependent Claim
30 words
The method of claim 9 , wherein the barrier metal is selected from a group comprising tantalum, tantalum nitride, tungsten nitride, titanium nitride, titanium silicon nitride, and tantalum silicon nitride.
Claim 13
Dependent Claim
26 words
The method of claim 9 , wherein depositing the barrier metal further comprises the acts of: chemical vapor depositing the barrier metal on the semiconductor substrate.
Claim 14
Dependent Claim
46 words
The method of claim 9 , further comprising acts of: depositing a low-k dielectric material on the polysilicon gate and source/drain regions formed adjacent the polysilicon gate; defining contact holes in the low-k dielectric material; and filling the contact holes with copper in a damascene process.
Claim 15
Dependent Claim
39 words
The method of claim 12 , wherein the act of filling the contact holes comprises the acts of: depositing a barrier metal in the contact holes; forming a copper seed layer; and electroplating copper to fill the contact holes.
Claim 16
Dependent Claim
26 words
The method of claim 9 , further comprising the acts of: depositing electroless metal on the polysilicon gate and source/drain regions formed adjacent the polysilicon gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-26 | 2006-02-25 | 2006-08-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-26 | 2010-02-25 | 2010-08-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-26 | 2014-02-25 | 2014-08-27 | $7700.00 | Window Closed / Lapsed |