Methods for fabricating MOS transistors with notched gate electrodes

Claim 2

1 . A method for fabricating a MOS transistor, comprising: forming a multi-layered insulation layer, including at least two insulation layers, on a substrate; patterning the multi-layered insulation layer to form an opening exposing a predetermined region of the substrate, wherein the opening has a stair-shaped sidewall such that an upper portion of the opening is wider than a lower portion of the opening; forming a gate insulation layer on the exposed substrate; forming a gate electrode filling the opening on the gate insulation layer; and removing the multi-layered insulation layer to form a gate electrode having a notch region under an edge portion thereof.

Claim 3

2 . The method as claimed in claim 1 , wherein the multi-layered insulation layer includes lower and upper molding layers, which are sequentially stacked.

Claim 4

3 . The method as claimed in claim 2 , wherein the lower molding layer includes a sacrificial layer and a lower insulation layer, which are sequentially stacked.

Claim 5

4 . The method as claimed in claim 2 , wherein the upper molding layer includes an etch stop layer, an upper insulation layer, a polishing stop layer, and a capping insulation layer, which are sequentially stacked.

Claim 6

5 . The method as claimed in claim 3 , wherein the sacrificial layer comprises a silicon oxide layer.

Claim 7

6 . The method as claimed in claim 3 , wherein the lower insulation layer comprises a silicon oxide layer formed to have a thickness ranging from 50 to 1000 Å.

Claim 8

7 . The method as claimed in claim 4 , wherein the etch stop layer comprises a silicon nitride layer.

Claim 9

8 . The method as claimed in claim 4 , wherein the upper insulation layer comprises a silicon oxide layer formed to have a thickness ranging from 500 to 3000 Å.

Claim 10

9 . The method as claimed in claim 4 , wherein the polishing stop layer comprises a silicon nitride layer.

Claim 11

10 . The method as claimed in claim 4 , wherein the capping insulation layer comprises a silicon oxide layer.

Claim 12

11 . The method as claimed in claim 2 , wherein the lower molding layer includes a sacrificial layer and a lower insulation layer, and the upper molding layer includes an etch stop layer, an upper insulation layer, a polishing stop layer and a capping insulation layer.

Claim 13

12 . The method as claimed in claim 1 , further comprising: forming a protecting spacer insulation layer on an entire surface of the substrate including the opening with the stair-shaped sidewall; and etching back the protecting spacer insulation layer to form a protecting spacer on a side of the stair-shaped opening.

Claim 14

13 . The method as claimed in claim 2 , wherein forming the opening having the stair-shaped sidewall comprises: patterning the upper molding layer using a mask pattern to form an upper opening exposing the lower molding layer; forming a self-aligned spacer on a side of the upper opening; and etching the lower molding layer using the self-aligned spacer as an etch mask to form a lower opening exposing a surface of the semiconductor substrate.

Claim 15

14 . The method as claimed in claim 2 , wherein forming the opening having the stair-shaped sidewall comprises: patterning the upper molding layer using a first mask pattern to form an upper opening exposing a surface of the lower molding layer; and patterning the lower molding layer using a second mask pattern to form a lower opening exposing a surface of the semiconductor substrate.

Claim 16

15 . The method as claimed in claim 3 , wherein forming the opening having the stair-shaped sidewall comprises: patterning the upper molding layer using a mask pattern to form an upper opening exposing the lower insulation layer; forming a self-aligned spacer on a side of the upper opening; etching the lower insulation layer using the self-aligned spacer as an etch mask to form a lower opening exposing the sacrificial layer; and removing the sacrificial layer using a cleaning process to expose a surface of the substrate.

Claim 17

16 . The method as claimed in claim 3 , wherein forming the opening having the stair-shaped sidewall comprises; patterning the upper molding layer using a first mask pattern to form an upper opening exposing a surface of the lower insulation layer; patterning the lower insulation layer using a second mask pattern to form a lower opening exposing a surface of the sacrificial insulation layer; and removing the sacrificial insulation layer using a cleaning process to expose a surface of the substrate.

Claim 18

17 . The method as claimed in claim 4 , wherein forming the opening having the stair-shaped sidewall comprises: patterning the capping insulation layer, the polishing stop layer, and the upper insulation layer using a mask pattern to form an upper opening exposing the etch stop layer; forming a spacer insulation layer on an entire surface of the substrate including the upper opening; etching back the spacer insulation layer until a surface of the lower molding layer is exposed such that a self-aligned spacer is formed; and etching the lower molding layer by using the self-aligned spacer as an etch mask to form a lower opening exposing a surface of the semiconductor substrate.

Claim 19

18 . The method as claimed in claim 4 , wherein forming the opening having the stair-shaped sidewall comprises: patterning the capping insulation layer, the polishing stop layer, and the upper insulation layer using a first mask pattern to form an upper opening exposing a surface of the etch stop layer; and patterning the etch stop layer and the lower molding layer using a second mask pattern to form a lower opening exposing a surface of the semiconductor substrate.

Claim 20

19 . The method as claimed in claim 5 , wherein forming the opening having the stair-shaped sidewall comprises: patterning the capping insulation layer, the polishing stop layer, and the upper insulation layer using a mask pattern to form an upper opening exposing the etch stop layer; forming a spacer insulation layer on an entire surface of the substrate including the upper opening; etching back the spacer insulation layer until a surface of the lower insulation layer is exposed such that a self-aligned spacer is formed; etching the lower insulation layer using the self-aligned spacer as an etch mask to form a lower opening exposing a surface of the sacrificial insulation layer; and removing the sacrificial insulation layer using a cleaning process to expose a surface of the substrate.

Claim 21

20 . The method as claimed in claim 5 , wherein forming the opening having the stair-shaped sidewall comprises: patterning the capping insulation layer, the polishing stop layer, and the upper insulation layer using a first mask pattern to form an upper opening exposing a surface of the etch stop layer; patterning the etch stop layer and the lower insulation layer using a second mask pattern to form a lower opening exposing a surface of the sacrificial insulation layer; and removing the sacrificial insulation layer using a cleaning process to expose a surface of the substrate.

Claim 22

21 . The method as claimed in claim 13 , wherein the self-aligned spacer comprises a silicon nitride layer formed to have a thickness ranging from 5 to 500 Å.

Claim 23

22 . The method as claimed in claim 15 , wherein the self-aligned spacer comprises a silicon nitride layer formed to have a thickness ranging from 5 to 500 Å.

Claim 24

23 . The method as claimed in claim 17 , wherein the self-aligned spacer comprises a silicon nitride layer formed to have a thickness ranging from 5 to 500 Å.

Claim 25

24 . The method as claimed in claim 19 , wherein the self-aligned spacer comprises a silicon nitride layer formed to have a thickness ranging from 5 to 500 Å.

Claim 26

25 . The method as claimed in claim 1 , wherein forming the gate electrode filling the opening on the gate insulation layer comprises: forming a gate conductive layer that sufficiently fills the opening; and planarizing the gate conductive layer using chemical mechanical polishing (CMP).

Claim 27

26 . The method as claimed in claim 25 , wherein the gate conductive layer is composed of at least one material selected from the group consisting of polysilicon, silicon germanium, cobalt, tungsten, titanium, and nickel.