US6566198B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture
Assignee: International Business Machines Corp
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Filing: 2001-03-29
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Granted: 2003-05-20
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Expires: 2021-03-29
Abstract
Abstract A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.
Inventors
- 👤 Heemyong Park
- 👤 Fariborz Assaderaghi
- 👤 Atul C. Ajmera
- 👤 Ghavam G. Shahidi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:42
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10D30/031; H10D30/0321; H10D30/0323; H10D30/6729; H10D30/6737; H10D30/674; H10D30/6741; H10D30/6743; H10D64/00; H10D64/01; H10D64/018; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
105 words
A method of forming a raised source/drain field effect transistor including the steps of: etching a gate region in a layer of silicon of a first thickness sufficient for silicidation of contacts, so that the gate region has a second thickness corresponding to a desired channel thickness, wherein the second thickness is less than the first thickness; oxidizing the gate region to form a sacrificial oxide layer; removing the sacrificial oxide layer; forming inside spacers after removing the sacrificial oxide layer; forming a gate structure at said gate region; and forming drain and source structures adjacent said gate structure in regions of said first thickness.
Claim 2
Independent Claim
105 words
A method of forming a raised source/drain field effect transistor including the steps of: etching a gate region in a layer of silicon of a first thickness sufficient for silicidation of contacts, so that the gate region has a second thickness corresponding to a desired channel thickness, wherein the second thickness is less than the first thickness; oxidizing the gate region to form a sacrificial oxide layer; removing the sacrificial oxide layer; forming inside spacers after removing the sacrificial oxide layer; forming a gate structure at said gate region; and forming drain and source structures adjacent said gate structure in regions of said first thickness.
Claim 3
Dependent Claim
33 words
The method of claim 1 , further comprising the steps of: implanting dopants in said layer of silicon of said first thickness; and diffusing said dopant into said region of said second thickness.
Claim 4
Dependent Claim
15 words
The method of claim 1 , further comprising the step of modulating said second thickness.
Claim 5
Dependent Claim
19 words
The method of claim 1 , wherein the second thickness is dependent on the length of the gate region.
Claim 6
Dependent Claim
19 words
The method of claim 1 , wherein the second thickness is dependent on the width of the gate region.
Claim 7
Independent Claim
132 words
A method of forming a raised source/drain field effect transistor, the method comprising the steps of: forming a silicon on insulator layer having portions that define first and second recesses on top and bottom surfaces, respectively, of said silicon on insulator layer such that the silicon between the recesses define a channel region; forming a buried oxide interface, having a top and a bottom surface, the top surface of the buried oxide interface having a raised portion that engages the second recess on the bottom surface of the silicon on insulator layer; forming elevated source and drain regions, the elevated source and drain being formed above the top surface of the silicon on insulator layer; and forming a gate in the recess on the top surface of the silicon on insulator layer.
Claim 8
Independent Claim
132 words
A method of forming a raised source/drain field effect transistor, the method comprising the steps of: forming a silicon on insulator layer having portions that define first and second recesses on top and bottom surfaces, respectively, of said silicon on insulator layer such that the silicon between the recesses define a channel region; forming a buried oxide interface, having a top and a bottom surface, the top surface of the buried oxide interface having a raised portion that engages the second recess on the bottom surface of the silicon on insulator layer; forming elevated source and drain regions, the elevated source and drain being formed above the top surface of the silicon on insulator layer; and forming a gate in the recess on the top surface of the silicon on insulator layer.
Claim 9
Dependent Claim
32 words
The method of claim 6 , further comprising the steps of: implanting impurities in the silicon on insulator layer; and activating the impurities so that the dopant redistributes into the channel region.
Claim 10
Dependent Claim
14 words
The method of claim 6 , further comprising the step of silicidating of contacts.
Claim 11
Dependent Claim
14 words
The method of claim 6 , wherein the raised portion results from oxide growth.
Claim 12
Dependent Claim
24 words
The method of claim 6 , wherein the dimensions of the raised portion of the buried oxide interface are dependent on the gate length.
Claim 13
Dependent Claim
15 words
The method of claim 10 , wherein the oxide growth increases as channel length increases.
Claim 14
Dependent Claim
24 words
The method of claim 10 , wherein the dimensions of the raised portion of the buried oxide interface are dependent on the gate width.
Claim 15
Dependent Claim
24 words
The method of claim 6 , further comprising the step of forming oxide spacers in the first recess of the silicon on insulator layer.
Claim 16
Dependent Claim
25 words
The method of claim 6 , wherein the elevated source and drain regions are formed by utilizing oxide spacers for gate source and drain isolation.
Claim 17
Dependent Claim
89 words
A raised source and drain field effect transistor comprising: a gate region in a layer of silicon of a first thickness sufficient for silicidation of contacts, said gate region having a second thickness corresponding to a desired channel thickness, wherein the second thickness is less than the first thickness; a gate structure at said gate region; drain and source structures adjacent said gate structure in regions of said first thickness; and a channel having the desired channel thickness uniformly over the entire distance between the source and drain structures.
Claim 18
Dependent Claim
89 words
A raised source and drain field effect transistor comprising: a gate region in a layer of silicon of a first thickness sufficient for silicidation of contacts, said gate region having a second thickness corresponding to a desired channel thickness, wherein the second thickness is less than the first thickness; a gate structure at said gate region; drain and source structures adjacent said gate structure in regions of said first thickness; and a channel having the desired channel thickness uniformly over the entire distance between the source and drain structures.
Claim 19
Dependent Claim
23 words
The raised source/drain field effect transistor of claim 15 , wherein the second thickness is dependent on the length of the gate region.
Claim 20
Dependent Claim
23 words
The raised source/drain field effect transistor of claim 16 , wherein the second thickness is dependent on the width of the gate region.
References Cited (Backward Citations)
US6022781A
Cited
US6051473A
Cited
US6307230B1
Cited
US6150244A
Cited
US6218711B1
Cited
US6228729B1
Cited
US6368927B1
Cited
US6395589B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-05-19 | 2006-11-18 | 2007-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-19 | 2010-11-18 | 2011-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-19 | 2014-11-18 | 2015-05-20 | $7700.00 | Window Closed / Lapsed |