US6560766B2
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Method and apparatus for analyzing a layout using an instance-based representation
Assignee: Synopsys Inc
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Filing: 2001-07-26
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Granted: 2003-05-06
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Expires: 2021-07-26
Abstract
Abstract One embodiment of the invention provides a system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout. The system operates by receiving a representation of the layout, wherein the representation defines a plurality of nodes that include one or more geometrical features. Next, the system converts the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout, wherein each node instance can be further processed without having to consider effects of external factors on the node instance. The system then performs an further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Inventors
- 👤 Christophe Pierrat
- 👤 Chin-Hsen Lin
- 👤 Yao-Ting Wang
- 👤 Fang-Cheng Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:46
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
123 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing further processing on the instance-based representation by processing each node instance only once, whereby the further processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 2
Independent Claim
123 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing further processing on the instance-based representation by processing each node instance only once, whereby the further processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 3
Dependent Claim
33 words
The method of claim 1 , wherein the layout can define at least one of: features on the semiconductor chip; and a mask that is used to create features on the semiconductor chip.
Claim 4
Dependent Claim
36 words
The method of claim 1 , wherein converting the representation into the instance-based representation involves: considering how interactions with other nodes affect each node; and considering how environmental attributes specified in the layout affect each node.
Claim 5
Dependent Claim
48 words
The method of claim 1 , wherein the layout includes a hierarchy of nodes; and wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.
Claim 6
Dependent Claim
36 words
The method of claim 4 , further comprising collapsing the hierarchy, so that each node in the hierarchy is represented by a node instance that is not affected by higher-level or neighboring nodes in the hierarchy.
Claim 7
Dependent Claim
52 words
The method of claim 1 , wherein performing the further processing involves performing a die-to-database inspection on the layout by: performing an initial die-to-database inspection on an image generated from a node instance; and subsequently performing die-to-die inspections between the image and other images generated from other occurrences of the node instance.
Claim 8
Dependent Claim
34 words
The method of claim 1 , wherein performing the further processing involves performing verification on the layout to verify that a simulated silicon image of a node conforms to a layout of a node.
Claim 9
Dependent Claim
28 words
The method of claim 7 , wherein the simulated silicon image of the node is generated by applying optical proximity correction or phase shift masking to the node.
Claim 10
Dependent Claim
60 words
The method of claim 1 , wherein performing the further processing involves performing proximity effect correction while generating a mask to be used in fabricating the circuit, whereby a correction can be calculated once for a given node instance, and the calculated correction can be applied to other occurrences of the given node instance without having to recalculate the correction.
Claim 11
Independent Claim
122 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing a defect analysis by, locating defects, and using the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.
Claim 12
Independent Claim
122 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing a defect analysis by, locating defects, and using the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.
Claim 13
Dependent Claim
36 words
The method of claim 10 , wherein converting the representation into the instance-based representation involves: considering how interactions with other nodes affect each node; and considering how environmental attributes specified in the layout affect each node.
Claim 14
Dependent Claim
48 words
The method of claim 10 , wherein the layout includes a hierarchy of nodes; and wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.
Claim 15
Dependent Claim
141 words
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the method comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 16
Dependent Claim
141 words
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the method comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 17
Dependent Claim
31 words
The computer-readable storage medium of claim 13 , wherein the layout can define: features on the semiconductor chip; or a mask that is used to create features on the semiconductor chip.
Claim 18
Dependent Claim
38 words
The computer-readable storage medium of claim 13 , wherein converting the representation into the instance-based representation involves: considering how interactions with other nodes affect each node; and considering how environmental attributes specified in the layout affect each node.
Claim 19
Dependent Claim
50 words
The computer-readable storage medium of claim 13 , wherein the layout includes a hierarchy of nodes; and wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.
Claim 20
Dependent Claim
41 words
The computer-readable storage medium of claim 16 , wherein the method further comprises collapsing the hierarchy, so that each node in the hierarchy is represented by a node instance that is not affected by higher-level or neighboring nodes in the hierarchy.
Claim 21
Dependent Claim
54 words
The computer-readable storage medium of claim 13 , wherein performing the further processing involves performing a die-to-database inspection on the layout by: performing an initial die-to-database inspection on an image generated from a node instance; and subsequently performing die-to-die inspections between the image and other images generated from other occurrences of the node instance.
Claim 22
Dependent Claim
36 words
The computer-readable storage medium of claim 13 , wherein performing the further processing involves performing verification on the layout to verify that a simulated silicon image of a node conforms to a layout of a node.
Claim 23
Dependent Claim
30 words
The computer-readable storage medium of claim 19 , wherein the simulated silicon image of the node is generated by applying optical proximity correction or phase shift masking to the node.
Claim 24
Dependent Claim
62 words
The computer-readable storage medium of claim 13 , wherein performing the further processing involves performing proximity effect correction while generating a mask to be used in fabricating the circuit, whereby a correction can be calculated once for a given node instance, and the calculated correction can be applied to other occurrences of the given node instance without having to recalculate the correction.
Claim 25
Dependent Claim
141 words
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the method comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing a defect analysis by, locating defects, and using the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.
Claim 26
Dependent Claim
141 words
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the method comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing a defect analysis by, locating defects, and using the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.
Claim 27
Dependent Claim
38 words
The computer-readable storage medium of claim 22 , wherein converting the representation into the instance-based representation involves: considering how interactions with other nodes affect each node; and considering how environmental attributes specified in the layout affect each node.
Claim 28
Dependent Claim
50 words
The computer-readable storage medium of claim 22 , wherein the layout includes a hierarchy of nodes; and wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.
Claim 29
Independent Claim
145 words
An apparatus that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the apparatus comprising: a receiving mechanism that is configured to receive a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and an processing mechanism that is configured to perform further processing on the instance-based representation by analyzing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 30
Independent Claim
145 words
An apparatus that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the apparatus comprising: a receiving mechanism that is configured to receive a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and an processing mechanism that is configured to perform further processing on the instance-based representation by analyzing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 31
Dependent Claim
29 words
The apparatus of claim 25 , wherein the layout can define: features on the semiconductor chip; or a mask that is used to create features on the semiconductor chip.
Claim 32
Dependent Claim
35 words
The apparatus of claim 25 , wherein the conversion mechanism is configured to: consider how interactions with other nodes affect each node; and to consider how environmental attributes specified in the layout affect each node.
Claim 33
Dependent Claim
48 words
The apparatus of claim 25 , wherein the layout includes a hierarchy of nodes; and wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.
Claim 34
Dependent Claim
43 words
The apparatus of claim 28 , further comprising a collapsing mechanism that is configured to collapse the hierarchy, so that each node in the hierarchy is represented by a node instance that is not affected by higher-level or neighboring nodes in the hierarchy.
Claim 35
Dependent Claim
53 words
The apparatus of claim 25 , wherein the processing mechanism is configured to perform a die-to-database inspection on the layout by: performing an initial die-to-database inspection on an image generated from a node instance; and subsequently performing die-to-die inspections between the image and other images generated from other occurrences of the node instance.
Claim 36
Dependent Claim
35 words
The apparatus of claim 25 , wherein the processing mechanism is configured to perform verification on the layout to verify that a simulated silicon image of a node conforms to a layout of the node.
Claim 37
Dependent Claim
28 words
The apparatus of claim 31 , wherein the simulated silicon image of the node is generated by applying optical proximity correction or phase shift masking to the node.
Claim 38
Dependent Claim
61 words
The apparatus of claim 25 , wherein the processing mechanism is configured to perform proximity effect correction while generating a mask to be used in fabricating the circuit, whereby a correction can be calculated once for a given node instance, and the calculated correction can be applied to other occurrences of the given node instance without having to recalculate the correction.
Claim 39
Independent Claim
141 words
An apparatus for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the apparatus comprising: a receiving mechanism that is configured to receive a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and a processing mechanism that is configured to, locate defects, and to use the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.
Claim 40
Independent Claim
141 words
An apparatus for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the apparatus comprising: a receiving mechanism that is configured to receive a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and a processing mechanism that is configured to, locate defects, and to use the instance-based representation to correlate defects with a specific node instance in order to determine if the specific node instance is prone to defects.
Claim 41
Dependent Claim
35 words
The apparatus of claim 34 , wherein the conversion mechanism is configured to: consider how interactions with other nodes affect each node; and to consider how environmental attributes specified in the layout affect each node.
Claim 42
Dependent Claim
48 words
The apparatus of claim 34 , wherein the layout includes a hierarchy of nodes; and wherein a given node in the hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the hierarchy.
Claim 43
Independent Claim
114 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; and performing further processing on the instance-based representation, wherein performing the further processing on multiple occurrences of a node instance involves performing the further processing on the node instance only once, and then applying results of the further processing to other occurrences of the node instance.
Claim 44
Independent Claim
114 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: receiving a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; converting the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; and performing further processing on the instance-based representation, wherein performing the further processing on multiple occurrences of a node instance involves performing the further processing on the node instance only once, and then applying results of the further processing to other occurrences of the node instance.
Claim 45
Independent Claim
117 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: generating an instance-based representation of a layout by identifying multiple occurrences of identical node instances in the layout; wherein the instance-based representation defines a plurality of nodes that include one or more geometrical features; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 46
Independent Claim
117 words
A method for analyzing a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, comprising: generating an instance-based representation of a layout by identifying multiple occurrences of identical node instances in the layout; wherein the instance-based representation defines a plurality of nodes that include one or more geometrical features; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and performing further processing on the instance-based representation by processing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 47
Independent Claim
152 words
A system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the system comprising: a processor; a memory; a receiving mechanism that is configured to receive a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and an processing mechanism that is configured to perform further processing using the processor on the instance-based representation by analyzing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
Claim 48
Independent Claim
152 words
A system that analyzes a layout related to a circuit on a semiconductor chip using an instance-based representation of a set of geometrical features that comprise the layout, the system comprising: a processor; a memory; a receiving mechanism that is configured to receive a representation of the layout; wherein the representation defines a plurality of nodes that include one or more geometrical features; a conversion mechanism that is configured to convert the representation into an instance-based representation by identifying multiple occurrences of identical node instances in the layout; wherein each node instance can be further processed without having to consider effects of external factors on the node instance; and an processing mechanism that is configured to perform further processing using the processor on the instance-based representation by analyzing each node instance only once, whereby the processing does not have to be repeated on multiple occurrences of the node instance in the layout.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-05-05 | 2006-11-04 | 2007-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-05 | 2010-11-04 | 2011-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-05 | 2014-11-04 | 2015-05-06 | $7700.00 | Window Closed / Lapsed |