Patent US6522584B1 successfully refreshed from Google Patents.
US6522584B1
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Programming methods for multi-level flash EEPROMs
Assignee: Round Rock Research LLC
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Filing: 2001-08-02
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Granted: 2003-02-18
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Expires: 2021-08-02
Abstract
Abstract A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.
Inventors
- 👤 Chun Chen
- 👤 Kirk D. Prall
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C16/00; G11C16/02; G11C16/04; G11C16/0483
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
154 words
A method for programming a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising: generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region; injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage comprising at least one gate voltage pulse; and applying the gate voltage for a period of time corresponding to a selected threshold voltage for the memory cell corresponding to a selected one of the programming states, wherein each selected threshold voltage corresponds to a different period of time.
Claim 2
Independent Claim
154 words
A method for programming a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising: generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region; injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage comprising at least one gate voltage pulse; and applying the gate voltage for a period of time corresponding to a selected threshold voltage for the memory cell corresponding to a selected one of the programming states, wherein each selected threshold voltage corresponds to a different period of time.
Claim 3
Dependent Claim
24 words
The method of claim 1 , wherein the gate voltage pulse has a pulse width of between approximately 1 ns and approximately 10 μs.
Claim 4
Dependent Claim
53 words
The method of claim 1 , wherein a transistor comprising a transistor control gate is connected in series between the drain region of the memory cell and a drain voltage generator, whereby a control voltage applied to the transistor control gate adjusts a voltage applied to the drain region of the memory cell.
Claim 5
Dependent Claim
75 words
The method of claim 1 , wherein a plurality of circuit segments are connected in parallel between the drain region of the memory cell and a drain voltage generator, each circuit segment comprising a resistor connected in series with a transistor having a transistor control gate, whereby selectively applying a control voltage to the transistor of at least one of the circuit segments adjusts a voltage applied to the drain region of the memory cell.
Claim 6
Dependent Claim
15 words
The method of claim 1 , wherein the drain current has a substantially constant magnitude.
Claim 7
Dependent Claim
20 words
The method of claim 1 , wherein a reverse back bias is applied between the substrate and the control gate.
Claim 8
Dependent Claim
35 words
The method of claim 1 , wherein the gate voltage comprises a single gate voltage pulse having a pulse width, and the period of time corresponding to the selected threshold voltage equals the pulse width.
Claim 9
Dependent Claim
40 words
The method of claim 1 , wherein the gate voltage comprises a plurality of gate voltage pulses each having a pulse width, and the period of time corresponding to the selected threshold voltage equals a sum of the pulse widths.
Claim 10
Dependent Claim
17 words
The method of claim 1 , wherein the gate voltage is the same for each programming state.
Claim 11
Dependent Claim
20 words
The method of claim 9 , wherein the magnitude of the gate voltage is the same for each programming state.
Claim 12
Dependent Claim
22 words
The method of claim 9 , wherein the gate voltage comprises a plurality of gate voltage pulses each having the same magnitude.
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