US5831901A
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Method of programming a memory cell to contain multiple values
Assignee: Monterey Research LLC
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Filing: 1996-11-08
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Granted: 1998-11-03
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Expires: 2016-11-08
Abstract
Abstract A method for programming multiple values in an individual flash memory cell is disclosed. An individual flash cell is programmed by holding the bit line, corresponding to the particular memory cell to a value, V d , while the voltage on the control gate, V g , of the memory cell is varied. By varying the voltage on the control gate, multiple values are stored in the memory cell. The resulting values are self-convergent, therefore, verify circuitry becomes unnecessary.
Inventors
- 👤 Yuan Tang
- 👤 Qimeng Zhou
- 👤 Hsingya Arthur Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C2211/00; G11C2211/56; G11C2211/562; G11C2211/5625
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
85 words
A method of programming a cell having a drain, a control gate, and a source positioned on a substrate with multiple data values, comprising the steps of: applying a voltage, v d , to said drain during the programming of a predetermined first data value of said cell; applying a predetermined voltage, v g , to said control gate of said cell, responsive to said predetermined first data value, during the programming of said cell; holding said substrate at ground potential; and floating said source.
Claim 2
Independent Claim
85 words
A method of programming a cell having a drain, a control gate, and a source positioned on a substrate with multiple data values, comprising the steps of: applying a voltage, v d , to said drain during the programming of a predetermined first data value of said cell; applying a predetermined voltage, v g , to said control gate of said cell, responsive to said predetermined first data value, during the programming of said cell; holding said substrate at ground potential; and floating said source.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein said voltage v d , has the value of approximately 8v.
Claim 4
Dependent Claim
23 words
The method of claim 1, wherein said voltage v g , has a value in the range of approximately 8v to approximately 10v.
Claim 5
Dependent Claim
113 words
In a flash memory cell having a source, a control gate coupled to a respective word line and a drain coupled to a respective bit line, a method of programming said flash memory cell comprising the steps of: applying a first voltage v d , to said respective bit line during the programming of a predetermined first data value; applying a second voltage, v g , to said respective word line, responsive to said predetermined first data value, during the programming of said cell; floating said source; applying a third voltage, v g , to said respective word line, responsive to a predetermined second data value; and holding a substrate at ground potential.
Claim 6
Dependent Claim
113 words
In a flash memory cell having a source, a control gate coupled to a respective word line and a drain coupled to a respective bit line, a method of programming said flash memory cell comprising the steps of: applying a first voltage v d , to said respective bit line during the programming of a predetermined first data value; applying a second voltage, v g , to said respective word line, responsive to said predetermined first data value, during the programming of said cell; floating said source; applying a third voltage, v g , to said respective word line, responsive to a predetermined second data value; and holding a substrate at ground potential.
Claim 7
Dependent Claim
16 words
The method of claim 4, wherein said voltage v d has the value of approximately 8v.
Claim 8
Dependent Claim
15 words
The method of claim 4, wherein said voltage v g has a plurality of values.
Claim 9
Dependent Claim
22 words
The method of claim 6, wherein said voltage v g has a value in the range of approximately 8v to approximately 10v.
Claim 10
Dependent Claim
108 words
In an array of memory cells formed on a substrate, a plurality of memory cells having a source, a drain and a gate, wherein a plurality of bit lines are connected to said respective plurality of drains, and wherein a plurality of word lines are connected to said respective plurality of gates, comprising the steps of: applying a voltage, v d , to a first bit line in said plurality of bit lines; applying simultaneously a respective plurality of voltages, v g , to said plurality of word lines, responsive to a respective plurality of data values; floating said respective sources; and holding said substrate at ground potential.
Claim 11
Dependent Claim
108 words
In an array of memory cells formed on a substrate, a plurality of memory cells having a source, a drain and a gate, wherein a plurality of bit lines are connected to said respective plurality of drains, and wherein a plurality of word lines are connected to said respective plurality of gates, comprising the steps of: applying a voltage, v d , to a first bit line in said plurality of bit lines; applying simultaneously a respective plurality of voltages, v g , to said plurality of word lines, responsive to a respective plurality of data values; floating said respective sources; and holding said substrate at ground potential.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-11-02 | 2002-05-04 | 2002-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-02 | 2006-05-04 | 2006-11-03 | $3760.00 | Window Closed / Lapsed |
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