US6091631A
Expired / Lapsed
US
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Program/verify technique for multi-level flash cells enabling different threshold levels to be simultaneously programmed
Assignee: Monterey Research LLC
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Filing: 1998-07-01
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Granted: 2000-07-18
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Expires: 2018-07-01
Abstract
Abstract A program/verify method for a multi-level flash memory array, wherein threshold values to be programmed into each flash memory cell are represented using binary bits. In the program/verify method for each cell, the most significant bit representing the threshold level to be programmed into a cell is read first and the cell is programmed to the minimum threshold level represented by the most significant bit. The next most significant bit is then read and if necessary further programming pulses are applied to complete programming. By programming to the level of the most significant bit first rather than programming to each possible threshold separately as determined by all bits read together, less time is required for programming an array.
Inventors
- 👤 Joe Kucera
- 👤 Joseph Skrovan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:02
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3454; G11C16/3459; G11C11/00; G11C11/56; G11C11/5621
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
185 words
A method of programming a multi-level flash memory cell to one of a plurality of threshold voltage (vt) levels as represented by a plurality of bits, the method comprising the steps of: (a) erasing the cell so that the cell has a threshold set to a lowest one of the vt levels; (b) determining if a state of a most significant one of the bits identifies a first maximum representable threshold value, and if so programming the cell to a first one of the vt levels before preceding to step (c); (c) determining if the state of a next most significant bit identifies a second maximum representable threshold value while a state of the most significant bit identifies less than the first maximum representable threshold value, and if so programming the cell to a second one of the vt levels; and (d) determining if the state of the most significant bit along with a state of the next most significant bit identify both the first and second maximum representable threshold values, and if so programming the cell to a third one of the vt levels.
Claim 2
Independent Claim
185 words
A method of programming a multi-level flash memory cell to one of a plurality of threshold voltage (vt) levels as represented by a plurality of bits, the method comprising the steps of: (a) erasing the cell so that the cell has a threshold set to a lowest one of the vt levels; (b) determining if a state of a most significant one of the bits identifies a first maximum representable threshold value, and if so programming the cell to a first one of the vt levels before preceding to step (c); (c) determining if the state of a next most significant bit identifies a second maximum representable threshold value while a state of the most significant bit identifies less than the first maximum representable threshold value, and if so programming the cell to a second one of the vt levels; and (d) determining if the state of the most significant bit along with a state of the next most significant bit identify both the first and second maximum representable threshold values, and if so programming the cell to a third one of the vt levels.
Claim 3
Dependent Claim
29 words
The method of claim 1, wherein the second vt level is less than the first vt level and the third vt level is greater than the first vt level.
Claim 4
Dependent Claim
131 words
The method of claim 1, further comprising the following steps: storing the most significant bit in a first latch (312) and the next most significant bit in a second latch (311) prior to the step (b); toggling the second latch (311) prior to step (c) if the most significant bit and the next most significant bit identify the third one of the vt levels, and utilizing the output of the second latch (311) to make the determination in step (c); and setting the first latch (312) after step (b) and prior to step (d) to indicate if the most significant bit and the next most significant bit represent the third one of the vt levels, and utilizing the value stored in first latch (312) to make the determination in step (d).
Claim 5
Independent Claim
243 words
A method of programming a flash memory cell to one of threshold voltage levels vt1, vt2 or vt3 as represented by binary bits stored in a first latch (311) and a second latch (312), wherein a verify procedure utilized during programming transitions a state of at least one of the first and second latches from a 0 to a 1 when programming is complete, the method comprising the steps of: erasing the cell so that the cell has a threshold below the threshold level vt1; determining if the second latch (312) stores a 0 and if so programming the cell to the threshold level vt2; toggling the second latch (312) so that the latch stores a 0 if the second latch (312) is storing a 1; reading the cell state to cause a 1 to be stored in the second latch (312) if the cell has a voltage level greater than the threshold level vt2 and the first latch (311) stores a 1; reading the cell state to cause a 1 to be stored in the first latch (311) if the cell has a voltage level greater than the threshold level vt2; inverting the state stored by the second latch (312); determining if the second latch (312) stores a 0 and if so further programming the cell to the threshold level vt3; and determining if the first latch (311) stores a 0 and if so programming the cell to the threshold level vt1.
Claim 6
Independent Claim
243 words
A method of programming a flash memory cell to one of threshold voltage levels vt1, vt2 or vt3 as represented by binary bits stored in a first latch (311) and a second latch (312), wherein a verify procedure utilized during programming transitions a state of at least one of the first and second latches from a 0 to a 1 when programming is complete, the method comprising the steps of: erasing the cell so that the cell has a threshold below the threshold level vt1; determining if the second latch (312) stores a 0 and if so programming the cell to the threshold level vt2; toggling the second latch (312) so that the latch stores a 0 if the second latch (312) is storing a 1; reading the cell state to cause a 1 to be stored in the second latch (312) if the cell has a voltage level greater than the threshold level vt2 and the first latch (311) stores a 1; reading the cell state to cause a 1 to be stored in the first latch (311) if the cell has a voltage level greater than the threshold level vt2; inverting the state stored by the second latch (312); determining if the second latch (312) stores a 0 and if so further programming the cell to the threshold level vt3; and determining if the first latch (311) stores a 0 and if so programming the cell to the threshold level vt1.
Claim 7
Dependent Claim
29 words
The method of claim 4, wherein the threshold level vt3 is greater than the threshold level vt2, and the threshold level vt2 is greater than the threshold level vt1.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-18 | 2008-01-17 | 2008-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-18 | 2012-01-17 | 2012-07-18 | $7700.00 | Window Closed / Lapsed |